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Volume 11 Number 15 August 1, 2007

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This Issue's Feature Articles

Gigabit Signal Integrity Creates New Challenges

By Guy Foster,

VP Outbound Marketing. SyntheSys Research Inc.
Product/Service Focus

This issue's focus is Bit Error Rate (BER) Tester
You can find many references to "bit error rate" at our web site.

What's New in Test
  7/30/2007 China taps Tektronix for DTV testing lab
  7/26/2007 STATS ChipPAC acquires LSI’s Thai test, assembly plant for $100M
  7/23/2007 Cypress shifts to 'labless' model with test facility sale
  7/23/2007 Sensors to give 'sight' to future cars
  7/19/2007 Teradyne reports second quarter, 2007 results
  7/19/2007 The iPhone Shakes the Consumer Electronics' Industry
  7/18/2007 Keithley Announces Joint Development Partnership with France's CEA Leti Laboratory
  7/18/2007 Synopsys acquires Mosaid mem tech, IP

Come to a One-Day Course

Cost Effective Tests Using ATE, DFT and BIST 

by Louis Y. Ungar in Beaverton, Oregon on August 6, 2007

Application Notes
  7/31/2007 Understanding electronic-device data sheets: A designer's imperative
  7/19/2007 Perform PSRR testing with analyzers having no dc-bias ports
  7/25/2007 If I Only Changed The Software, Why Is the Phone on Fire?
Case Study
  7/27/2007 Inside Apple's iPhone: More than just a dial tone
Conference Article
  7/17/2007 Semicon West speaker highlights critical test challenges
FREE Giveaways
  7/27/2007 Free DVD on industry defects study and Agilent Medalist x6000 AXI
  7/18/2007 Designing Next Generation Test Systems
Magazine Article
  7/31/2007 Are your board designs testable?
  7/23/2007 Ridgetop Group Announces Availability of a Sensor for Real-Time Detection of Solder-Joint Faults
  7/19/2007 Analyzer tests reverse-recovery behavior of diodes
  7/19/2007 Moore's Law under fire again
  7/19/2007 Uncertainty principle: Time and frequency in high-speed digital design
  7/19/2007 When Intel speaks, do chip test execs listen?
  7/16/2007 Choose the right signal generator for your apps
  7/16/2007 Save on field-support costs with PBL methods - built-in diagnosis

Come to a Three-Day Course

Random Vibration and Shock Testing, HALT, ESS, HASS

in Santa Barbara, California on August 20-22, 2007

Product Releases
  7/31/2007 Four-channel jitter tolerance test tool debuts
  7/31/2007 Software eases digital RF test signal creation
  7/30/2007 Agilent Introduces Dual-Purpose 8 Gb/s Fibre Channel SAN Tester and Protocol Analyzer
  7/30/2007 New Custom Function Module streamlines integration of Boundary-Scan with Teradyne TestStation
  7/26/2007 NI unrolls low-cost 6.5-digit multimeter for PXI
  7/26/2007 Teradyne introduces DC90XP for automotive and power management markets
  7/25/2007 GOEPEL electronic: New Diagnostic Concept for ECUs enables very easy Adaptation and Application
  7/25/2007 Keithley intros 6.5-digit USB digital multimeter
  7/25/2007 New diagnostic concept enables very easy adaptation and application
  7/25/2007 System keeps drivers from the wrong lane
  7/24/2007 Agilent Technologies’ Time-To-Digital Converter Delivers Exceptional Performance For Precise Timing-Measurement Applications
  7/24/2007 Pickering introduces new PXI RF switching solutions
  7/23/2007 Aeroflex unveils radio test set for TETRA, P25
  7/23/2007 BER, noise measurement tool adds enhancements
  7/20/2007 Picture quality analyzer uses Human Vision Model
  7/19/2007 Handheld instrument identifies optical fiber faults
  7/19/2007 Handheld XRF analyzer touts improved detection limits
  7/19/2007 Unisoft ProntoTEST-FIXTURE software translates CAD and Bill of Materials (BOM)
  7/19/2007 Yield-enhancement tool protects IP
  7/18/2007 Digital Phosphor Oscilloscopes (DPOs) deliver more signal information for faster design
  7/17/2007 FormFactor's Khandros touts R&D results - MEMS-based probing contact
  7/17/2007 GL releases enhanced BERT application
  7/17/2007 Keithley Introduces LINUX-Based Parametric Test System
  7/17/2007 LXI gains Measure Foundry support
  7/17/2007 Pickering Interfaces introduces two new LXI matrix switching solutions
  7/17/2007 Software test suite rolls for 3GPP LTE products
  7/17/2007 Suss MicroTec unveils new ProbeShield technology
  7/17/2007 Verigy debuts V5000ep for small production runs
  7/16/2007 CAN Communication Module with highest Functionality now available on USB basis

Come to a Three-Day Course

Design for Testability and for Built-In Self Test

by Louis Y. Ungar in St. Louis, MO on October 22-24, 2007

  7/26/2007 IEEE Forms Study Groups to Explore Creation of Standards Based on VSI Alliance Technology
Web postings
  7/31/2007 Optimizing Automated Test Applications for Multicore Processors with NI LabVIEW
  7/16/2007 Acceptable "reject rate" for hand assembly
  7/16/2007 Multiple Test Strategies for Testing Today’s Complex Boards
Gigabit Signal Integrity Creates New Challenges

By Guy Foster,

VP Outbound Marketing. SyntheSys Research Inc.

It is well documented that many parallel data transfer architectures used in computing have switched over to higher speed serial data streams at Gigabits/sec. Examples include graphics card data (PCI to PCI Express) and storage communications (Parallel ATA to Serial ATA). The telecommunications industry has dealt with these higher speeds for a lot longer, but has not been forced to meet such stringent cost constraints. By engineering down to a competitive price, serial bus standards do not enjoy use of exotic microwave materials, nor are they allowed significant performance margins to make links work. A decade or two ago, signals with these frequency components would have been carried in waveguides, but to pass them across the types of circuit board materials of an average motherboard, engineers have had to get creative.

The Implications for Test

As is usual, testing falls into two main types:
• Compliance
• Troubleshooting

Transmitter Compliance Testing

The nature of compliance testing is changing as the signals evolve and available margins are reduced. Gigabit transmitter compliance testing has traditionally been carried out through use of a sampling scope eye diagram mask as shown in Figure 1. However, these have proven to be inadequate predictors of system performance and it is increasingly common for standards to require a mask to be passed at the BER level that the system is expected to achieve. This is beyond the ability of a simple sampling scope mask to verify.

Figure 1 - BER Based Eye Diagram Mask - (To see figure click for Adobe version)

A second area of interest in transmitter testing relates to the ingenuity of techniques used to overcome low cost circuit board materials. It is increasingly common for transmitter output stages to boost the high frequency content of the signal in order to overcome frequency dependent loss resulting from the material. With such de-emphasized signals the first bit of a sequence of identical bits is at a higher amplitude than subsequent bits, and requires separate mask tests for the first bit and subsequent de-emphasized bits. See Figure 2.

Figure 2 a) Transition bit mask test and b) Deemphasized bit mask test

Receiver Compliance Testing

Changes are also occurring in receiver testing. Although in telecoms it has been traditional to test the clock recovery function of a receiver with sinusoidal jitter, serial buses have mainly avoided testing the receiver whenever possible. As rates in that arena reach 5 Gb/s, such avoidance is no longer an option. Whereas telecom testing focused on testing the clock recovery function of a receiver only, recent standards are also requiring that the decision function be tested through the addition of other eye closure elements to form an often complex stressed eye test recipe.  See a typical equipment set up for receiver compliance testing in Figure 3.

Figure 3 – Typical Receiver Stress Setup

Clocking Schemes

Another area that is getting more focus is clock distribution for serial bus architectures. Gigabit telecom links have traditionally used an embedded clock scheme with each data stream having dedicated clock recovery. Computer standards have employed this architecture, but also forwarded and distributed clock systems. For these latter schemes, different test methods are required. One key parameter for schemes where a low speed (e.g. 100MHz) clock is multiplied up to Gb/s rates is to measure the Phase Locked Loop, PLL, bandwidth and peaking. As many motherboards have hostile environments that cause the incoming clock to be ‘dirty’, the multiplier’s ability to reduce jitter is important and needs to be measured accurately. It is also useful to measure the jitter spectrum of clock and data to measure spectrally banded jitter values to aid troubleshooting.  See Figure 4.

Figure 4 – a) PCI Express Clock Multiplier Jitter Measurement, b) Spectrally Integrated Jitter Measurement for Gb/s Data Rate

A final note on clocking is the now well known use of spread spectrum clocking (SSC) to circumvent FCC regulations on interference, shown in Figure 5. The idea is that dithering the system clock frequency with a ~30kHz modulation reduces the measured emissions, even though the instantaneous power is unchanged. Our experience of measuring devices equipped with SSC is that this can be a common source of compliance test failures. It is therefore useful to be able to examine the behavior of the modulation directly to verify performance.

Figure 5 - Spread Spectrum Clocking (SSC) Waveform Measurement


In the early stages of designing a new product, and later if compliance issues are discovered, the ability to dig deeper is vital. We have come across numerous examples where bit error ratio (BER) measurement has been essential to uncovering the whole picture. One example is of a memory IC that developed problems when the test process exercised its ability to deal with a lowered power supply voltage. An internal logic block started to fail at reduced voltage, but the chip’s output stage continued to function correctly. The result was an output waveform that was unchanged, and the fact that the perfectly formed eye diagram was composed of bits that were just plain wrong would never have been visible in a scope-only measurement. See Figure 6.  Similarly, we have helped customers making stressed eye measurements with alternative solutions track back the causes of their device failures to their test equipment being overstressed – another example of the value of measurement depth.

Figure 6 – Poor BER Performance Invisible on an Eye Diagram


As the cost-sensitive computing industry joins the telecoms sector in employing Gb/s data rates, the nature of testing is evolving to cope with the unique requirements of this segment. We’ve looked at some of those changes to compliance testing, and briefly touched on the topic of troubleshooting. More detail on all of the above, and also details of products that enable such testing are available on

Guy Foster
VP Outbound Marketing
SyntheSys Research Inc.
3475-D Edison Way
Menlo Park, CA 94025
Telephone: +1 (650) 364-1853 

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