Introducing
The Testability Director Version 3.2
 

The State of Memory Testing

 By:  

IEEE P1581 Offers Solutions for Board Level Memory Test Problems

By: Heiko Ehrenberg, GOEPEL Electronics USA

You will be linked directly to the listings you select below after you have  logged in. If you are not logged in, go to http://www.besttest.com/Register/disclaimer.cfm 

This issue's focus is Memory Testing. 
You can view and add to our existing list of Test Products/Services, Test Literature, Test Definitions, Test Vendors, containing "GPIB"

Come to the tutorial

Cost Effective Tests Using ATE, DFT and BIST

by Louis Y. Ungar at APEX on February 18, 2007 

Visit A.T.E. Solutions, Inc. on January 22-26, 2007 at 
Measurement Science Conference - Booth #444 

and win an iPod

An ancient philosopher once said, "The only constant is change." The computer memory industry is certainly no different. Since we wrote an article about memory testing for the Best Test Newsletter (see “How to Select a Memory Tester”, August 16, 2004), computer memory has become even more complex, with greater size and faster operating speeds. These changes make testing memory before installation even more critical.

The most important change is the switch from DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory - you can see why the industry simply refers to it as DDR!) to DDR2 SDRAM. In a nutshell, DDR2 is capable of running at a much higher frequency and lower power than DDR. In our prior article we wrote, “Windows XP computers are typically shipping with memory modules operating at 333 MHz or faster.” Two years later, common DDR2 modules operate at twice the bus speed of older DDR technology, which substantially improves overall computer performance.

However, DDR2 memory modules capable of running at 667 MHz and 800 MHz have issues not seen in older DDR modules. Individual DDR2 chips come in BGA (Ball Grid Array) packages while DDR chips are usually the TSOP (Thin Small Outline Package) format. BGA requires a far more complex soldering process during the manufacturing stage than older TSOP packages, which means that more stringent testing is required to spot memory faults. Aluminum spreaders are commonly mounted on DDR2 modules since the higher frequencies generate a great deal of heat, although DDR2 uses smaller page sizes than DDR1 to reduce power. DDR2 also operates at a lower operating voltage than older DDR1 designs and require more control circuitry. These traits make DDR2 far more complex, and while DDR2 isn’t necessarily more prone to failure than older memory formats, more stringent testing is required in order to weed out defective memory.

The second change is the upcoming consumer release of Vista, Microsoft’s new Windows operating system. Consumer reviews have been mostly positive, but all reviewers agree that Vista is a “memory hog” that requires at least 1 GB of main memory in order to run efficiently. This means that an average PC running Vista will require at least twice the memory of a PC running Windows XP. This is obviously good news for the memory industry eager to sell more product! But larger 1 GB and 2GB modules (up from 256 MB and 512 MB just 2 years ago) demand more exhaustive testing since the increase in cells and the more complex wiring also increases the chance for faults.

Computer techs have a number of free tools at their disposal to test DDR2 modules, such as the Windows Memory Diagnostic software available from Microsoft. It allows you to test memory directly on a motherboard by booting up the software via floppy disk or CD.

While testing memory directly on a motherboard may be a good solution for some, it is not an acceptable solution for those who need to regularly test memory. Testing via the motherboard frequently takes hours per stick of memory and the motherboard socket is not made for constant insertion/removal. If you break the socket, you’ve severely damaged the motherboard!

Fortunately, dedicated memory testers are available for quickly testing large volumes of memory. Such dedicated testers range in price from less than $1,000 to over $1 million. On the simplest level, such testers use complex algorithms to check for problems such as shorts in the wiring and cell interference.  They also run tests at different voltage levels and frequencies. More expensive testers are used for exhaustive testing, and include increasingly complex test algorithms and even temperature stress chambers.

Small, low-cost standalone testers are sufficient for most users and catch the vast majority of faults. (See RAMCHECK DDR2 for an example.) Their low cost means that manufacturers, dealers and data centers can acquire a number of testers and spread them throughout each facility. However, it is important to note that low-cost testers are not meant to be used as certifying testers! Memory used in mission-critical sectors such as defense and aerospace, or testing done during the early stages of the manufacturing process, must use high-end test equipment made specifically for this purpose. Since testers can be major investments, it is important to make sure the unit is upgradeable and expandable. The tester vendor should provide frequent firmware upgrades and “swappable” adapters to extend the life of the tester beyond just the current memory types.

New memory technology is on the horizon, making it likely that even more complex testing will be required. DDR3 will be appearing on the market within a year or so. But what will follow DDR3? There are no guarantees - except change - but the odds favor increasingly complex memory that requires even more stringent testing.

 Heiko Ehrenberg, GOEPEL Electronics USA

To be competitive in today's world market, electronics manufacturers are pressured to produce more products of better quality in shorter time for lower cost. To achieve this goal, all manufacturing stages have to be optimized, including test. To keep the cost of test and the cost of repair low, reliable and guaranteed detection and localization of structural faults at board and system level in the shortest possible time is top priority. This includes all circuitry on the Unit Under Test, including connections to memory devices.

Testing connectivity to memory devices in functional test may not be possible or may not yield the needed diagnostic resolution. The development of functional test software is very time consuming and therefore costly, especially when good diagnostics are a requirement. Furthermore, if a board or system does not boot up, functional tests cannot be executed at all.

The only other option to electrically test memory device connectivity at pin level is through In-Circuit Test or - if access from an In-Circuit Test fixture is not available - through IEEE-Std.1149.1/Boundary Scan. Both also have limitations that need to be overcome in order for board and system level test technology to keep up with the ever increasing complexity of memory devices.

Memory device manufacturers in general have steadily resisted implementing IEEE-Std. 1149.1 in their devices. The IEEE P1581 working group is defining a new standard for static component interconnection test, dramatically simplifying the test of memory interconnects. With the defined test architecture embedded in memory devices, the memory cell structure is completely bypassed; a simple, combinatorial test circuitry implemented into the memory device is used instead to link input and output signals during test mode. A controlling device (typically an IEEE 1149.1 compliant component connected to the memory device) applies a stimulus to the input pins and observes the output pins of the device under test. The benefits of this methodology, which eliminates the need for functional memory access cycles during memory connectivity tests, include very simple test pattern, few test vectors, very short test execution time, full diagnostic capability for structural faults, and a simple Design for Testability implementation in the device under test.

Memory Cluster Testing with Boundary Scan access

Today, Boundary Scan connectivity test at board and system level frequently includes memory devices (typically referred to as Memory Cluster Test). Even though such memory devices often times don't have IEEE 1149.1 resources built-in, connectivity to them can be tested by using 1149.1 access to their address, data, and control signals from the controlling device (e.g. a CPU, FPGA, DSP, or ASIC).

Traditional memory cluster test at board and system level is based on functional device models. These models describe the pin functionality as well as the write, read, and other access cycles for a particular memory device. The host/master component connected to the memory device uses the model to write test pattern to the memory and then to read back that pattern, in an attempt to detect and diagnose any structural faults on the memory pins (opens, shorts, stuck-at-0/1). Typically, a "walking 1" and "walking 0" pattern set is written to the address signals, a walking data pattern is written using a counting address pattern, and so on, and the data is read back from the memory to verify the write operations. If the correct data is read back, access to the memory appears to be without failures. If not, the data actually read can provide diagnostic information about the defect (the actual test pattern depends on the ATPG software, which uses CAD information to automatically generate the test).

Introducing IEEE P1581

In an attempt to overcome problems with memory cluster test based on functional device models, the IEEE P1581 working group is defining a protocol and architecture for static component interconnection test. This standard is being developed to define a test strategy to be implemented in complex memory devices which do not support IEEE 1149.1. It describes a simple means to verify the memory I/O pin connectivity (address, data, and control signals). In a test mode operation, the memory cell structure is completely bypassed; a combinatorial test circuitry implemented into the memory device is used instead to link input and output signals. The control of whether the device is to be tested or in normal operation is accomplished with either some Test Mode Control logic or with an optional Test Pin as defined in the IEEE P1581 proposal (for details regarding Test Mode Entry and Exit, as well as the actual test logic implemented in a P1581 compliant device, please contact the working group). A controlling device (typically an IEEE 1149.1 compliant component connected to the memory device) applies a stimulus to the input pins and observes the output pins of the device under test.

The Combinatorial Test Logic embedded into a P1581 compliant device consists of a simple XOR/XNOR structure or Inverters and other logic gates, linking memory input pins to output pins so that each output is connected through the test logic to a unique set of inputs. One of the most important aspects of the P1581 architecture is that a connection error on one of the pins will not inhibit the test of other pins.

For more information on Memory Cluster Test or to request a white paper on IEEE P1581, please contact the working group  or write to h.ehrenberg@ieee.org

• If your friend forwarded this newsletter to you, please register as a member and receive The BestTest Newsletter -- absolutely free!
• If you wish to update your news preferences or cancel the subscription, please unsubscribe.
• If you have any questions, please email experts@BestTest.com

Get the widest selection of test related books and software at the BestTest Online Store.

Find any text on test. Search the topic below:

Search Now: