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S.R.
Sabapathi, Technical Director and CEO of Qmax
What follows is a case study involving the test of
a highly complex circuit board, the HF Receiver MCU Board displayed in
Figure 1. The article describes the variations of test
methodologies and equipment needed to test such a board.
High Density Device Packages and reduced test access
Today's PCBs are quite complex in nature, populated with components such as PQFP / BGA package CPU, DSP, ASIC, FPGA, Flash RAM, Dual port RAM and discrete devices as compared to standard Dual in Line or low pin density components of previous technologies.
Complex VLSI and ASIC Devices
ASIC devices typically do not come with sufficient internal structural or functional details, BGA devices and high-density QFP packages are difficult to access for test. CPU based boards require a unique test methodology.
Test challenge in PCB Functional Test and Diagnosis
To test boards containing a variety of these components with reasonable fault coverage is a challenge for most Board Test ATEs available in the market today. No single test methodology can meet all these test requirements. Hence a new generation ATE system is needed, which can support multiple test methodologies.
The PCB in Figure 1 used in a military RADAR system, populated with various components mentioned above. The objective is to functionally test it Off-Line and if it fails, diagnose faults to the faulty node or component. The Desired Fault coverage is 95% or greater of certain fault types.
Figure 1- HF Receiver MCU Board
Multiple Test Strategy
A detailed study of the HF Receiver MCU Board schematics revealed that different tests should be created for different blocks of the PCB, each with the most suitable test methodology. As a result, various access methods need to be used for test fixtures, including: bed of nail contacts, edge connector access, a JTAG port and even Test Clips and Probes. The blocks we created for test purposes are as follows:
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CPU Block- 80286 CPU (PQFP Package) with its core logic
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DSP Block with its Flash RAMs, Dual port RAMs and associated
logic
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FPGA Blocks
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CODECs / ADCs / Timing Devices
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Logic and mixed signal devices
Testing a CPU based board in a Board Functional Tester is always a challenge and to do so at real clock speed is even more
challenging. With Design for Testability (DFT), some circuits can eliminate the CPU during test by keeping it in Hi-Z mode while the rest of the board is being tested. Force Driving the CPU in this manner requires that the ATE have such capabilities and CPU pins should be accessible for physical contact. Of course the CPU device must be capable of this operation. For example, older generation CPUs may not have Hi-Z mode.
Use of Boundary Scan or In-Circuit Emulator ports are simple alternatives to test rest of the board by using the CPU pins as virtual test pins and drive / sense through JTAG / ICE ports. But many of the older generation CPUs do not support Boundary Scan or ICE ports. Even so Boundary Scan tests / ICE tests are like static functional test and cannot run at real CPU speeds thus leaving the possibility of not detecting timing related problems as faced in real world.
This case study used Qmax's patented
Bus Cycle Signature System (BCSS).
BCSS is used to learn the digital signatures of every node in the CPU logic and compare on a faulty board to detect the failing node. This method did not require complex test program generation or expensive CPU simulation models.
View a typical test sequence here.
Test Sequences
The following test sequences were used to test the circuit board of Figure 1:
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Open / Short Test for Test Fixture contact verification.
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Voltage Measurement Test to verify the On-Board generated voltages.
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Frequency measurement tests on various Oscillators On-Board.
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Card Edge Functional Test for Analog MUX, Digital POT and NOR Gates.
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Bus Cycle Signature System Tests for Processor on board and its associated logic devices.
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Integrated Boundary Scan Test for DSP and associated RAMS and ROMS
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In-circuit Functional Test for devices accessible only through through test clips on board
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VI Trace tests for LSI timing chip (ASIC - No details), XC3042A (No BS Support),
CODEC- AD 1843JS and FPGA (ASIC
- No Details, No BS Support).
These tests are sequenced in an order that can provide the earliest possible diagnose of faults that may affect tests later on in the sequence.
A total of 34 tests were made in order to cover all circuitry and components in the MCU Board to achieve fault coverage of 96%.
A brief description of the test sequences is given below:
Power-off Test
Open / Short Test: Scans the Test Fixture with Board Under Test Loaded to detect any opens (contact problems with bed of nails or edge connector fixtures) and to detect any shorts between nails or nodes such as VCC and GND.
Measurement of RLC: System should be capable of measuring RLC values using a 0.5V stimulus signal so that no diode or transistors are turned on during such measurements. Guarding is
optional.
Measurement of Nodal impedances (VI Trace): In addition to Open / Short tests and RLC measurement, VI Trace (Voltage
- Current Curve) tests can detect subtle change in the nodal impedances, diode drop values and characteristic impedance changes and thus can detect faults even before the power is applied to the board under test.
Power-on Tests
Measurement of Voltages and Clock Frequencies: All supply voltages applied to the board and those voltages generated on board are tested. Clock frequencies can be measured with a 1Hz resolution and with user programmed threshold voltage levels.
Card Edge Functional Tests: Board's edge connectors are used to drive test logic pattern into the board using the ATE
system's physical test pins and it's output response is tested against either
simulator's expected output response, against learnt responses from a known good board, or against a predefined output response. Increased use of ASICs, FPGAs, DSPs, and CPU devices on board and the great expense of device models for simulation, Learn
- Compare technique is a cost effective alternative. Edge Functional Test can also include testing of analog and mixed signal portion of the board if the ATE is equipped with analog drive and sense channels synchronized with digital channels.
You can view
the Mixed Signal Test - Wave Form Editor.
Bus Cycle Signature Test: This test methodology is patented by Qmax and
is most useful for CPU based boards. The method employs learn and compare of digital signatures. There is no need to write complex test programs or expensive simulation models. This technique uses the Built-in Self-Test routines of the boot-up ROM to exercise the board under test. It learns the digital bit stream generated on every node and compresses them as a 32-bit signature. A CPU specific POD is required for generation of Bus Cycle Test Windows and strobes to be placed during Data Valid time of each bus cycle. It is possible to isolate faults down to node level.
Integrated Boundary Scan Test: The Integrated Boundary Scan -
Card Edge Test can check interconnection between Boundary Scan devices and edge pins and as well as carry out functional test. Use of
Qmax's unique Graphical Wave Form editor, for both Edge pins (50 Ohms or Force driving physical test pin) and Boundary Scan pins (Virtual Test Pin) to easily configure functional test routines for Non-Boundary Scan devices in the cluster. The Graphical wave editor complier automatically routes test vector data for physical test pin to ATE pin drivers and for virtual test pin to JATG port with hassle free user interface. This unique test technique also provides for guided probe back tracking for detecting fault origin. You
can view an Integrated Boundary Scan Card Edge Wave Form
Editor.
In-Circuit Functional Test: These are In-Circuit Tests using Force Drive pin drivers of the ATE system and using the built in library routines for standard devices. These tests are performed for those devices that are not accessible through edge pins. They are also used when it is too difficult or cumbersome to write a test program to access these
devices' input pins blocked by preceding complex logic. Such Isolated component test increases fault coverage, while reducing the time taken to generate the test programs.
QSM VI: This is a VI trace technique fine tuned by Qmax. It is a learn and compare technique for detecting subtle changes in the nodal impedance of a device or node. Considering the high reliability of
today's devices, especially high density devices, the most likely fail modes are due to an external force such as static, over load or short circuit. In such cases the damaged input or output pins change their nodal characteristics and thus can be easily captured in QSM VI Trace tests. The added advantage in QSM VI technique is its moving reference test capability (any-pin-to-any-pin) and user defined test stimulus application. The technique is most useful for those devices, where no data is available.
Diagnostics tests- Automated Guided Probe back tracking facility: Card Edge Functional tests using ATE digital pin drivers and Boundary Scan Virtual Test pins have the capability to back track the origin of fault using the Guided Probe Back Tracking utility. One has to enter or import the netlist and should have learnt (if using Learn method) or verified (if using simulator) the internal
node's output response. Tagging of Schematics and Board Layout will ease the work of a test operator while probing for back tracking and works as a paperless test solution and thus providing greater security of technical data such as schematics and layouts.
Optional Tests for increased Fault coverage
At times, a board that passes a functional test in the ATE lab fails to work in the field and is returned to lab. Such occurrences can be considerably reduced if additional tests like DC and AC Parametric test are performed on the ATE.
Measurement of DC Parameters: A device whose input pins are accessible from the edge connector can be checked to ensure that its input Bias current is within specified limits. This helps reduced field returns as boards that pass functionally may not necessarily work in the field as a result of excess leakages in its input pins, as leakages on one board may overload other boards in the system. Similarly, output pins at the card edge can be tested for their fan-out capabilities. Also, if Tri-State leakage current of a PCB¡¦s I/O pin exceeds specifications, it may disturb the working of other PCBs in the system.
Measurement of AC Parameters: Testing frequency, pulse width, propagation delay, rise/fall times, event counters, etc. helps increase fault coverage for those boards with timing problems.
The time taken to run the above all tests in succession was about 5 minutes, which is quite acceptable in Repair / Maintenance environment for delivering test coverage of 96%.
The above tests were conducted in Qmax's ATE QT2256-320PXI.
About the author
Mr. S.R. Sabapathi, Technical
Director and CEO of Qmax a leading
manufacturer of Automated Test Equipment for Board Functional test,
has about 30 years of experience in PCB and Semi-con Test. His unique
test methodology, Bus Cycle Signature Test, for testing of CPU based
boards, had been patented in US,
UK
, Australia Singapore. Qmax’s presence in most country’s defense
establishments speaks its testimony.
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