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Volume 11 Number 12 June 16, 2007

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This Issue's Feature Articles

Test and Tester Software – Features and Technologies for Today’s ATE Systems

By Mike Dewey,

Sr. Product Manager, Geotest, Inc.

Reconfigurable Tester Resources for Extended JTAG/Boundary Scan Applications


Heiko Ehrenberg, Manager of US Operations, GOEPEL Electronics
Product/Service Focus

This issue's focus is Test Software
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What's New in Test
  6/14/2007 Teradyne is first to join Global Supply Chain Forum in China
  6/13/2007 Agilent completes acquisition of Adaptif Photonics
  6/6/2007 Is Cadence thinking of traversing the private route?
  6/1/2007 Corelis's growth provides job opportunities for test professionals

Come to a Three-Day Course

Random Vibration and Shock Testing, HALT, ESS, HASS

in Bellevue, Washington on July 10-12, 2007 

Application Notes
  6/1/2007 Testing signals for UWB aerospace systems
Magazine Articles
  6/17/2007 Digital-debugging methods save time
  6/13/2007 Using tolerance analysis method in product selection
  6/1/2007 A Nanotechnology Test System
  6/1/2007 Boundary scan stars in (high-definition) HD conferencing
  6/1/2007 Cable Test Extends Outside the Box
  6/1/2007 Certification Testing of Wi-Fi Mobile Devices
  6/1/2007 Critical Requirements for Next Generation Modeling and Simulation Tools
  6/1/2007 How much inspection data should you save?
  6/1/2007 Launch-off-shift at-speed test
  6/1/2007 Monitoring System Speeds Up Emission Testing
  6/1/2007 Spectrum analyzers respond to digital modulation
  6/1/2007 The Role of Vibration Testing in Product Integrity
  6/1/2007 Verifying 2-D Data Matrix Codes

Come to a Three-Day Course

Design for Testability and for Built-In Self Test

by Louis Y. Ungar in Boston, MA on July 23-25, 2007 

Product Releases
  6/15/2007 Systems enable fast, easy semiconductor characterization
  6/14/2007 Analog Devices debuts tri-axis inertial measurement unit
  6/14/2007 Digitizer card streams data to disk or display
  6/14/2007 NSX 100 inspection system finds macro defects
  6/14/2007 PXI Express tools offer up to 400MBps data streaming
  6/12/2007 Willtek’s 2303 Stabilock is the first TETRA tester for service
  6/11/2007 AC/DC Current Probes For Scopes Handle Up To 500 A
  6/11/2007 Quantum video tester ensures HDMI V1.3 compliance
  6/7/2007 Agilent introduces PCIe-GPIB interface card
  6/6/2007 Rohde & Schwarz demos differential measurement, debuts analyzers, etc.
  6/6/2007 Test suite steps up carrier Ethernet reliability
  6/5/2007 Multifunctional tester simplifies signal analysis
  6/6/2007 Panelists predict EDA and semiconductor challenges of 2017
  6/5/2007 Metrology, inspection equipment market in recovery
Web postings
  6/4/2007 It's Time To Lift The Burden From Logic Designers
  6/1/2007 Adopting the Right Solution for Embedded Memory Test
  6/1/2007 Logic BIST Scheme for Intra-/Inter-clock-domain At-Speed Testing
  6/1/2007 The Role of Memory Built-in Self Test and Built-in Self Diagnostics in Today's Overall Test Strategy
Test and Tester Software - Features and Technologies for Today's ATE Systems

By Mike Dewey,

Sr. Product Manager, Geotest, Inc.


Today’s ATE systems can be comprised of a complex collection of hardware and software technologies. Unlike past generation test systems that may have relied on a proprietary architecture and test language, today’s test systems are largely built on standardized languages and tools – providing test system designers and architects a high degree of flexibility but also presenting new challenges when integrating various hardware and software components.

Simply picking a test language and a hardware test platform that are compatible is only part of the process when architecting the overall test software for a system. Today’s test needs require that the system designer consider a much broader set of requirements and capabilities. Key features to consider as part of a test system include:

·       Easy program development, creation of User Interfaces (UIs), and easy program maintenance

·       An open architecture that supports a variety of hardware and software standards

·       An infrastructure that offers overall test management of all key parts of the program development, maintenance and run-time components

·       Wizards and tools that allow developers to focus on creating test programs rather then creating the environment to create test programs


Test systems that are being developed and deployed today are normally viewed as having two major components:

-       an application development environment (ADE), which includes the language and debug environment used to develop specific tests and

-       a test executive which provides all of the non-specific test infrastructure. This includes features such as data logging, management of user privileges and log-ins, management of test flow, and revision control / archiving of test programs. Test executives have been part of ATE system architectures for well over 20 years with the earliest ones being part of the proprietary software environments offered with ICT and functional test platforms produced by GenRad, Teradyne, Schlumberger, and others.

With the move to more open standards, however,  the mainstream acceptance of open hardware architectures and the use of different ADE’s,  users began to develop their own test executives.  Many times, these test executives were more of an after thought – created by using the ADE and providing only limited features for a specific application. In the past, test organizations have developed their own test executive, only to realize that building a test infrastructure to test their products may not be the best use of their programming resources. As a result, today’s functional test organizations are turning to off-the-shelf test management platforms that offer all of the required test executive features as well as an open architecture that can accommodate a wide variety of ADE’s.

First and foremost, today’s test management platform must offer users a ready to run environment. Test developers do not have the time to develop their own test executive.  Their focus today is on developing tests, integrating these tests, and verifying / releasing the complete test program. Time spent developing non-test components is time not spent developing UUT specific test code. An off-the-shelf test management platform needs to offer developers the ability to retain any current software investment while providing the needed infrastructure to support overall test execution and test program management, without expending man months or man years to create an overall test development / management environment.

Today’s Test Software Requirements and Features

Modern test management platforms or test executives offer several key attributes and features that help developers create and deploy applications quickly and efficiently:

·      Open architecture that can support a variety of software technologies and languages including ATEasy, LabView, CVI, C, .Net assemblies and classes, COM ActiveX components, DLLs, header files, and others. By providing the flexibility to import and use various languages, a user’s existing investment in test code is retained and can be reused for new systems or applications. Additionally, the use of these various ADEs is simplified by offering tools that automate the importing of files such as C header files, Vis and FPs.

·       Support for a variety of external instrument drivers including VXI plug and play function panels (.fp) and IVI-C / IVI-COM drivers. Even with the advancement and adoption of driver standards, a software platform still needs to have the flexibility to work with a variety of standards, since not all instruments may employ the same driver technology.

·      A UI development environment with features and capabilities specifically focused for supporting test and measurement applications as well as offering a touch panel interface for production test applications.

·      An open hardware control architecture for supporting a variety of interfaces, including VXI, PXI, TCP/IP, LXI, GPIB, and PCI. With today’s focus on the creation of hybrid systems that combine a variety of instrument interfaces, it is essential that a test management platform support a variety of control interfaces.

·      Flexible test sequencing is a key feature of the test executive and the ability to easily run / debug individual tests, a sequence of tests, or the complete program without creating or modifying code. This feature offers users an efficient and usable development environment.

·      An integrated data logging environment that is fully integrated with the test executive and requires no additional programming offers an effortless way to create a data log of some or all executed tests. In addition, with the broad acceptance of HTML formatted data, today’s test management products need to support not only text but also HTML formatted log files.

·      Support for ATML format.  With increasing support of ATML by various industry / government working groups, modern software platforms need to offer the ability to support the exporting and importing of ATML based data and/or programs.


Many developers of functional test systems today are turning to commercial test executive products to create and support their specific test needs. These products provide users with the ability to integrate many diverse components and technologies. And by including features such as wizards, code completion, and automatic initialization, the test developer is able to develop applications more quickly and efficiently.  By selecting a test executive, such as Geotest’s ATEasy, (available for a 30-day free evaluation) developers will find that they are able to focus their efforts on creating tests as opposed to creating a test development environment for the creation of tests.  

Reconfigurable Tester Resources for Extended JTAG/Boundary Scan Applications

Heiko Ehrenberg, Manager of US Operations, GOEPEL Electronics

Boundary Scan (often also referred to as JTAG) as defined in IEEE Std. 1149.1 has been adopted by many design and test engineers as test methodology for prototype verification and for production testing. Although being very successful, this technology has its share of limitations, some of which can be overcome with newer test standards, such as IEEE 1149.4 and IEEE 1149.6. Still, practically all electronic products contain some mixed-signal and and analog circuitry that is not testable with Boundary Scan. The typical answer is to test these parts of the circuitry with Functional Tests. Another approach, at least for some of those applications, would be to create Extended Boundary Scan tests that combine Boundary Scan with functional test capabilities based on reconfigurable tester hardware.

Boundary Scan access requires the test pattern to be transmitted serially through a Boundary Scan Chain that links the Test Access Ports (TAP) of the IEEE 1149.1 compliant devices on the UUT. As a result of this serial test pattern transmission, the rate with which test pattern is applied or sampled on Boundary Scan I/O pins is a function of the maximum test frequency and the length of the Boundary Scan chain. Typical update/sample rates are in the kilohertz range. Because of this limited throughput on device I/O pins, Boundary Scan is not suitable for most at-speed functional tests. However, with some ingenuity one can create many so called cluster tests that verify at least part of the UUT's functionality. For example, it is possible to use a Boundary Scan input cell to verify whether or not a clock signal is toggling, even though it would not be possible to determine the frequency of the clock signal with Boundary Scan access alone.

Many designs include some interface circuits, such as USB, RS232, RS485, Ethernet, and others. A pure Boundary Scan cluster test for such interfaces may not be possible or may be limited in the diagnostics it can provide. Automated test equipment with complementary test resources for these standard interfaces can support a more thorough functional test of this part of the UUT circuitry. Combining such functional test resources with Boundary Scan access on the UUT results in “Extended Boundary Scan” test applications for the verification of this kind of mixed-signal circuitry, with the benefit of simple test development and very good test coverage. One such approach of combining Boundary Scan with mixed-signal test capabilities has been introduced by GOEPEL Electronics in 2006 with the VarioCore technology for the company's SCANFLEX I/O modules.

VarioCore enables dynamic reconfiguration of SCANFLEX I/O modules with special Intellectual Property (IP) to support a wide range of test capabilities in the same hardware setup. In one customer application, the DLR Institute of Robotics and Mechatronics utilizes VarioCore for both the dynamic verification of sensors and the stimulation of sensor interfaces as independent IEEE 1149.1 test runs. The Unit Under Test is a docking tool for sensor guided satellite capturing, attached to a servicing satellite, and supports the autonomous docking of telecommunication satellites in geosynchronous orbit. Several docking tool sensors ensure the collision free insertion into the apogee motor nozzle of the client satellite, prior to the final docking.

The hardware tests are based on GOEPEL's SCANFLEX platform. After executing traditional Boundary Scan test and device programming applications, VarioCore enabled SCANFLEX I/O modules are reconfigured with specific VarioCore-IPs to be used as multi-channel frequency generator and frequency counter, respectively. Initially, the I/O modules support extended Boundary Scan interconnect tests, after reconfiguration they are utilized for combined Boundary Scan and Functional Tests. Further external instruments are no longer required, reducing the test adapter wiring considerably.

VarioCore is great for extending the reach of Boundary Scan into the mixed-signal realm and to create functional cluster tests for a UUT's interface circuitry. Yet, a complete, at-speed Functional Test is still needed to verify the overall functionality of the UUT. Such a Functional Test can rely on the test results of previous Boundary Scan tests, though, which verified proper connectivity of at least major parts of the UUT. Hence, at-speed Functional Tests can concentrate on just that – verifying that the UUT works at advertised.

As opposed to running Boundary Scan tests and Functional Test as separate applications, one can also combine the two, utilizing Boundary Scan access to circuit nodes to support Functional Test routines. Boundary Scan access can simplify the control and observation of certain circuit nodes and improve diagnostics and debugging capabilities especially in cases where Functional Test fails due to a CPU not being able to boot up properly.

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Cannot Duplicate
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