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Volume 11 Number 11 June 1, 2007




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This Issue's Feature Articles

Adopting the Right Solution for Embedded Memory Test

By Steve Pateras

Sr. Director of Strategic Technology, LogicVision Corporation

 

Logic BIST Scheme for Intra-/Inter-clock-domain At-Speed Testing

By Ravi Apte, Ph.D.

VP Strategy and Business Development, SynTest Technologies, Inc.

 

The Role of Memory Built-in Self Test and Built-in Self Diagnostics in Today's Overall Test Strategy

By Luigi Ternullo

Product Marketing Manager, STAR Memory System, Virage Logic Corporation
Product/Service Focus

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Design for Testability and for Built-In Self Test

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Report
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  5/16/2007 Boundary Scan Skews Test Coverage Tradeoffs in your Favor
  5/16/2007 Design for Boundary Scan Testability Beyond Static Connectivity Tests
  5/16/2007 Using JTAG to Preserve Board Level IP
Adopting the Right Solution for Embedded Memory Test

 By Steve Pateras

Sr. Director of Strategic Technology, LogicVision Corporation

Embedded memories represent a significant and growing percentage of today’s systems-on-a chip (SoCs) and as a result, memory built-in-self-test (BIST) and yield optimization solutions have gained significant importance.

In its simplest form, memory BIST consists of an on-chip engine placed next to each embedded memory that writes algorithmically generated patterns to the memory and then reads these patterns back to discover and log any defects. Over the years, memory BIST solutions have evolved to very sophisticated automation and intellectual property (IP) solutions to deal with today’s complex design and test challenges. Several important capabilities should be evaluated when choosing a memory BIST solution to ensure a cost-effective memory test strategy.

Design Automation

Many of today’s designs have literally hundreds of memories of different types and sizes spread throughout the chip. Adding test and repair capabilities to these memories can be a daunting task, requiring a comprehensive automation flow. With such a large number of memories on a chip, it becomes necessary to share BIST engines across multiple memories. The optimum allocation of BIST engines to memories depends on several factors, including the physical location of the memories, the clock domains within which the memories reside, the power ratings of the memories, the size and type of each memory, and the maximum desired test time. A key automation capability is the ability to take these factors into consideration and configure each BIST engine to support the memories allocated to it and create an optimal allocation of BIST engines to memories.  Having this kind of automation can reduce memory BIST integration time on large designs from days to hours.

Test Algorithm Programmability

Continued decreases in process feature sizes and associated increases in memory densities are resulting in a growing number of memory defect types. Many of these new defect mechanisms are difficult to predict and are therefore difficult to test. These defects are increasingly being discovered during the production testing of a device or, worse, during the analysis of field returns. This can result in significant quality and cost issues if the predetermined test algorithm used by the BIST engine does not detect a newly discovered defect type. In many cases, functional tests have to be added to the manufacturing test flow at significant cost. Because of this growing problem, some commercial memory BIST solutions now provide programmable BIST engines. With these engines it is possible to download (on the tester or in system) program code that implements an arbitrary memory test algorithm that can be applied to specific memories to test for new defect mechanisms.

Built-in Self Repair

To improve yields, embedded memories are being fitted with spare elements – spare rows, columns or both. These spare elements can be used to replace corresponding faulty elements and salvage the memory. The manufacturing flow for supporting a memory repair strategy can be expensive. During wafer sort, memories not only have to be tested, but all failure information must be extracted and analyzed to determine if the memory is reparable and how to repair it. Once the necessary repair information is calculated, the wafer containing the bad die must be moved to a laser repair station to blow the necessary fuses for each bad die. The wafer must then be retested to ensure all the repairs were successful. Alternatively, the good and repaired die can be sliced and packaged and sent to final test for verification. In the latter case, there will be additional (and expensive) final test fallout, as some unsuccessfully repaired die will have been packaged. Advanced commercial memory BIST solutions such as the ETMemory solution from LogicVision now support a fully embedded memory repair flow. This approach, referred to as built-in self-repair (BISR), can significantly reduce the complexities and costs described above. The most advanced BISR solutions test and permanently repair all defective memories in a chip using no external resources. Central to ETMemory is the concept of a programmable fuse pool. Electrical or programmable fuses are smaller than laser-based fuses and can be programmed without the need of any external equipment. Pooling of fuses is also becoming popular to reduce overhead. Because most memories will typically need little to no repair on any given die, sharing a pool of fuses for all memories allows for much better fuse utilization. Memories needing little to no repair require little to no fuse information to be stored.

To simplify the fuse data allotment, standard data compression techniques are used to implicitly allocate the necessary amount of fuse storage per memory. With ETMemory a fuse box controller performs on-chip management of a centralized programmable fuse pool. This controller, along with one or more BIST engines, performs all necessary activities for testing and repairing memories. In this solution the BIST engines are enhanced not only to test the memories, but also to analyze how to repair faulty ones. This capability is typically referred to as built-in repair analysis (BIRA). The solution also supports incremental repair. That is, the fuse data stored in the fuse pool can be used as a baseline on every power-on-reset. The BIST engines are then used to detect any new failures, and the combined fuse data is stored in a local BISR register to repair the memories. This approach allows for improving long term device and end-system reliability.  

Diagnostics

The ability to precisely and efficiently diagnose memory failures is a key component of understanding and correcting yield issues. A highly automated memory diagnostic approach is a key ingredient of an embedded memory strategy. The most advanced diagnostic solutions consist of both an IP and software component. The IP component refers to additional capabilities within the BIST engine for the logging of failure data. The most common of these is a “stop-on-error” capability. This enables the BIST engine to stop on the detection of each error so all pertinent failure information, such as the failing row and column addresses, can be scanned out of the engine and logged on the tester. Making use of this embedded diagnostic capability can be a significant challenge without appropriate automation. Correctly generating the necessary tester patterns to control all of the stop-on error activity within a specific BIST engine connected to a specific memory can be both time consuming and error prone. For this reason, a diagnostic solution that also incorporates control software running directly on the tester is highly beneficial. For example, the ETDiagnostic solution from LogicVision automatically handles all interactions with the BIST engines and processing of failure data. No test patterns need to be generated and no tester fail data output has to be processed or analyzed.

Conclusion

A number of aspects must be considered when choosing and implementing an embedded memory test and yield management solution. Adopting the right solution can result in significant cost and time-to-market savings.

More information on test and diagnosis of embedded memories can be found at www.memorybist.com and www.logicvision.com

Logic BIST Scheme for Intra-/Inter-clock-domain At-Speed Testing

By Ravi Apte, Ph.D.

VP Strategy and Business Development, SynTest Technologies, Inc.

1. Introduction

Logic Built-In Self-Test (BIST) schemes based on STUMPS structure use on-chip circuitry to generate test stimuli and analyze test responses, with little or no help from an ATE. The STUMPS (Self-Test Using a MISR and Parallel Shift register sequence generator) structure applies pseudo-random patterns generated by a PRPG (Pseudo-Random Pattern Generator) to a full-scan circuit in parallel and compacts the test responses into a signature with a MISR (Multiple-Input Signature Register). This approach has such advantages as simple test interface, better test quality, lower test cost, and higher reliability.

Due to its conceptual simplicity, logic BIST has been used successfully for many years for designs with a single clock or with multiple synchronous clock domains. This usage has been primarily based on the true value of logic BIST that is in realizing at-speed testing of high-speed and high-performance circuits. When designs contain multiple, high-speed, asynchronous clocks, most logic BIST schemes face many practical hurdles, i.e. test frequency manipulation, control complexity, implementation difficulty in minimizing clock skew etc. SynTest patented proprietary technology resolved these practical hurdles and TurboBIST-Logic product was introduced in 2001.

With usage of submicron technologies growing rapidly, need for at-speed testing is also becoming more acute. The most critical yet difficult part of logic BIST is how to detect intra-clock-domain faults and inter-clock-domain faults thoroughly and efficiently with a clocking scheme for proper capture of results. There have been three major at-speed timing control methods in existence. The launch-from-shift with capture alignment method aligns the rising edges for all capture pulses. The launch-from-shift with last-shift alignment method aligns the rising edges for all last-shift pulses. And the one-hot method conducts capture for one clock domain at a time. These methods, however, suffer from at least one the following issues: (1) the frequencies for all clock domains are required to satisfy certain relations, (2) some scan enable signals must be designed as a high-speed signal, (3) capture-disabling circuitry has to be added to prevent crossing clock-domain logic from affecting each other in capture mode, (4) control circuitry is complex, (5) only a synchronous circuit is targeted, and (6) test time is long.

This article introduces a new, powerful method using SynTest patented fundamental technology, with flexibility of the logic BIST scheme and easy of physical implementation it provides, to achieves true at-speed test quality for intra-clock-domain faults and inter-clock-domain faults in any multi-clock circuit.

SynTest Logic BIST Architecture

The BIST architecture, illustrated in Fig. 1, (shown for a 2 clock domain design) for testing the BIST-ready core consists of a TPG (Test Pattern Generator) for generating test stimuli, an input selector for providing pseudo-random or top-up ATPG patterns for the core-under-test, a TRA (Test Response Analyzer) for compacting test responses, a clock gating block for generating test clocks from original or functional clocks, and a BIST controller for coordinating the whole BIST operation. The self-test operation is initiated by asserting the Start signal, its end is indicated by the Finish signal, and its result is shown by the Result signal. When required, a standard IEEE 1149.1 Boundary-Scan interface is used for loading initialization and configuration data or for downloading internal states for fault diagnosis.

Fig. 1  Logic BIST Architecture. 

The BIST-ready core is “full-scan” circuit that must meet all scan design rules with additional circuitry for preventing bus conflicts at tri-state buses and for disabling asynchronous set/reset signals as well as false paths. It must also meet all BIST-specific design rules, such as for X-blocking and for test point insertion (TPI).

The TPG and TRA circuitry consists of PRPG-MISR pairs for each clock domain and avoids additional design efforts for clock skew management. Linear phase shifters, PS1 and PS2, (or space expanders, SpE1 and SpE2) are used to reduce the length of PRPGs, whereas space compactors, SpC1 and SpC2, are used to reduce the length of MISRs.

The test timing control circuitry consists of a BIST controller and a clock-gating block. The inputs to the clock-gating block are system clocks CK1 and CK2, which become CCK1 and CCK2 after going through some buffers. In addition, the clock-gating block is controlled by signals from the BIST controller to generate test clocks TCK1 and TCK2. The waveforms of TCK1 and TCK2, especially in capture mode, play a critical role in determining the test capability and physical implementation easiness of the logic BIST scheme.

1.1     Intra-Clock-Domain Fault Detection

Intra-clock-domain fault detection is relatively easy by using an ordered sequence of capture clocks for all clock domains in each capture window. For each clock domain, a single clock pulse is used to detect structural faults in low-speed testing, while two at-speed clock pulses are used to detect timing-related faults in at-speed testing. TurboBIST-Logic uses the double-capture scheme as it detects not only timing-related faults but also structural faults.

An example of at-speed test timing control is shown in Fig. 2, where test clocks TCK1 and TCK2 are staggered and generated by the clock-gating block shown in Fig. 1. In the capture window shown in Fig. 2, two capture pulses are generated for each clock domain. The last shift pulse and the first capture pulse (C1 or C3) are used to create transitions at the outputs of some scan cells; responses to the transitions are then caught by the second capture pulse (C2 or C4), where d2 and d4 are set based on functional clock frequencies. Thus, true at-speed testing is guaranteed to detect timing-related delay faults since no test clock frequency manipulation is conducted. 

Fig. 2  Timing Control Using Staggered Double-Capture.

Note that delays d1 and d5 in Fig. 2 can be adjusted as long as needed, so that one can use a global, slow scan enable (SE) signal to drive all clock domains. This significantly eases the physical implementation of the logic BIST scheme.

1.2     Inter-Clock-Domain Fault Detection

Inter-clock-domain fault detection is more complex, especially for timing-related delay faults. Fig. 3 shows four timing waveforms for detecting inter-clock-domain faults from the clock domain driven by TCK1 to the clock domain driven by TCK2.

Fig. 3  Inter-Clock-Domain Fault Test Timing

For testing structural faults, delay d is adjusted to be larger than the clock-skew between the two clock domains. This adjustment is easy. For detecting timing-related delay faults, delay d is further adjusted to satisfy the specified timing relation between the two clock domains. The waveform of Fig. 3 can achieve higher inter-clock-domain fault coverage since a pattern of higher randomness is applied and no fault effect caught in the immediate test response is masked out.

1.3     Capture Clock Generation

In order to generate an ordered sequence of double-capture clocks, the daisy-chain clock-triggering technique is used since it is more suitable for testing asynchronous designs. The daisy-chain clock-triggering technique means that the completion of the shift-in operation triggers the SE signal to become 0, switching operation mode from shift to capture. This in turn triggers the generation of two at-speed clock pulses for the first clock domain, the rising edge of the second capture clock pulse triggers the generation of two at-speed clock pulses for the second clock domain, and so on. Finally, the rising edge of second capture clock pulse for the last clock domain triggers the SE signal to become 1, switching operation mode from capture to shift. An example timing waveform is shown in Fig. 4.

Fig. 4  Daisy-Chain Clock-Triggering.

Conclusions

An at-speed logic BIST scheme based on SynTest patented technology is presented using an ordered sequence of capture clocks for testing designs containing multiple clock domains. The scheme employed is most suitable for testing of intra- as well as inter-clock-domain faults in asynchronous designs to achieve true at-speed test quality without any clock frequency manipulation. Physical implementation becomes easier due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements.

References

L.-T. Wang, X. Wen, P.-C. Hsu, S. Wu, and J. Guo, “At-Speed Logic BIST Architecture for Multi-Clock Designs,” Proc. ICCD-2005, pp. 475-478, October 2005.

B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, and S. Wu, “At-Speed Logic BIST for IP Cores,” Proc. IEEE/ACM Design Automation, and Test in Europe, pp. 860-861, Munich, Germany, March 2005.

The Role of Memory  BIST Built-in Self Test and Built-in Self Diagnostics
in Today's Overall Test Strategy

 By Luigi Ternullo

Product Marketing Manager, STAR Memory System, Virage Logic Corporation

Built-In Self-Test (BIST) has taken a larger role in today’s overall test strategy over time and has come to satisfy a significant need by enabling the testability of embedded components in System-on- Chip (SoC) designs in a very efficient manner.  Without the capabilities enabled by BIST, test coverage and/or test time of several embedded components would be severely impacted.  The need to facilitate testability for embedded components has lead to the development of interface standards and vector formats such as 1149.1 and WGL respectively, which in turn has helped to foster the continued adoption of BIST in the over all test strategy of SoCs. 

Leveraging BIST as part of a test strategy can have many advantages. In addition to improved coverage of embedded components and reduced test time due to efficient patterns, some of the advantages of BIST also include reduced pin count interface, reduced vector size, quick pattern bring up at the ATE, and system speed testing when used in conjunction with one chip clock multipliers such as a Phase Lock Loop. BIST satisfies several needs required for manufacturing test of embedded components, but manufacturing test is not the only component in the overall test strategy of a product.  In an ideal world, a design using a BIST strategy will enter manufacturing, work the first time, and never have any yield or testability issues.  Realistically this is not the case. Silicon issues always seem to occur and the majority of these silicon issues seem to manifest themselves in embedded memories. Embedded memories could be referred to as the canary in the coal mine, or the weakest link in SoC designs, because memories are typically developed with very aggressive design rules.  If there is a problem with the air in a coal mine, the canary will be the first to be affected.  Likewise, when there is an issue in silicon that affects yield, it will more than likely manifest itself in one or more embedded memories. The fact that memories are designed with aggressive design rules make them the weakest link, but the very nature of a memory is to have a regular structure, which also makes it the easiest to isolate silicon issues. 

Most silicon related issues are typically not catastrophic and do not result in no or low yields.  However, all SoCs are not created equal and do not yield the same way. The slightest yield loss will affect profitability, and therefore provisions must be put in place to ensure that profitability can be regained when silicon issues occur.  Because most yield related issues that manifest themselves in silicon will typically be observed in embedded SRAMs, provisions can be made to ensure that these issues can be detected and isolated for yield analysis.

Built-In Self Diagnostics (BISD) solutions are now being merged with BIST solutions in order to satisfy the need for enabling the analysis of silicon issues that manifested in embedded memories. The BISD capabilities may include pattern and algorithm programmability, as well as the required logic, to enable observability. The combined BIST and BISD solution is flexible enough to enable an optimized go, no-go manufacturing test that will satisfy the needs of volume production and have the ability to control and isolate silicon issues, while providing a means to diagnose silicon issues.   

Combining a BIST solution with BISD capabilities for embedded memories may seem straight forward, but to create a solution that includes optimal features and is area efficient requires some knowledge and understanding of how to test and diagnose embedded memories. For these reasons, design and test engineers must consider several factors when selecting a combined BIST and BISD solution. The simplest form of a BISD solution can enable some form of bitmapping capability. This capability is usually sufficient when the strategy is to isolate stuck faults in memories.  However, studies have shown that more soft failures will appear in designs manufactured in 65-nanometer (nm) and below.  Soft failures are defined as failures that will sporadically appear only under certain operating conditions. 

A more advanced BISD engine and test strategy is required to enable isolation of soft failures, which comes at a slight penalty in area.  Therefore, design and test engineers must be given the flexibility to choose between a basic BISD engine and an advanced BISD engine in order to successfully optimize area and the overall product test strategy.

Virage Logic’s STAR Memory System™ is an embedded test and repair solution that gives users the option to select between a basic BISD engine, in conjunction with BIST, and an advanced BISD engine.  The basic engine offers the capability to modify the pattern and generate a bitmap, while the advanced engine allows users to manipulate the embedded SRAM in several ways to better isolate elusive faults.  For more information on the STAR Memory System, go to www.viragelogic.com, or visit Virage Logic in booth #5578 at the Design Automation Conference in San Diego www.dac.com.

Since BIST, with the inclusion of BISD, is now playing a much larger role in the overall test strategy of today’s SoCs and the driving force is the need to ensure profitability in a very competitive industry, designers must better leverage the embedded testing of memories to help isolate issues that may occur in silicon. To enable BISD in an optimal fashion, the overall test strategy must be carefully evaluated and key decisions must be made in the design phase. This process requires the involvement of design and test engineering to ensure an optimal product strategy, which will ultimately lead to improved profitability.

 
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If you would like to include an exclusive article on how to best select Test and Tester Software, please contact LouisUngar@ieee.org.
 

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Events/Announcements

2007-2008

6/12 - 6/14
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
6/25 - 6/27
   Design for Testability and for Built-in Self Test
8/6
   Cost Effective Tests Using ATE, DFT and BIST
9/17 - 9/21
   AutoTestCon 2007
6/3 - 6/6
   Semiconductor Wafer Test Workshop (SWTW 2007)
6/3 - 6/8
   IEEE MTT-S/International Microwave Symposium
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   44th Design Automation Conference
6/7
   Agilent Technologies Showcases New Medalist x6000 Automated X-ray Inspection System
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   Sensors Expo & Conference
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   International Metrology Congress
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   International GHz/Gbps Test Workshop (GTW 07)
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6/19 - 6/22
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   LXI Consortium General Meeting
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   Successful Lead-Free RoHS Strategies Conference – Do it Right, Do it Now
6/20 - 6/22
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6/21 - 6/24
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   High Frequency Measurements Course
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   EMC Symposium
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   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
7/16 - 7/20
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7/29 - 8/2
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9/19 - 9/21
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10/7 - 10/11
   SMTA International 2007
10/9 - 10/11
   LXI PlugFest and General Meeting
10/9 - 10/11
   Asian Test Symposium (ATS’07)
10/10 - 10/12
   IPC Executive Market & Technology Forum
10/11 - 10/13
   Workshop on RTL and High Level Testing
10/22 - 10/24
   IPC Executive Market & Technology Forum
10/22 - 10/23
   IEEE Product Safety Engineering Society Symposium
10/23 - 10/25
   International Test Conference 2007
10/24 - 10/26
   Automotive Testing Expo North America
10/30 - 10/31
   NEPCON East
11/4 - 11/9
   Antenna Measurement Techniques Association (AMTA) Symposium
11/6 - 11/8
   Aerospace Testing Expo 2007 - North America
11/6 - 11/8
   Vision
11/6 - 11/8
   Bohai Electronics Week
11/7 - 11/9
   International High-Level Design, Validation and Test Workshop
11/11 - 11/13
   National Quality Education Conference
11/13 - 11/16
   Productronica
11/27 - 11/28
   TestForum 2007
12/5 - 12/6
   IP Based SoC Design Conference & Exhibition
4/1 - 4/3
   Printed Circuits Expo®, APEX® and the Designers Summit Conference
Definitions
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