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An A.T.E. Solutions, Inc. Internet Publication
Volume 10 Number 4 March 1, 2006
 

 

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This Issue's Feature Articles

Dynamic Burn-In of High Pin Count Logic Devices with Monitoring Capability
By:

Stephen Tsun, Sales Manager, INCAL Technology

 

Optimize Your Burn-In Design
By:
Randy Spivey, Randy@ceibis.com, VP Sales & Marketing, CEIBIS

Product/Service Focus
This issue's focus is Burn-In Products and Services. You can view and add to our existing list of Test Products/Services, Test Vendors, Test Literature, Test Definitions
What's New in Test
Announcements
  3/1/2006 BestTest and A.T.E. Solutions, Inc. to give away iPod at Measurement Science Conference
  2/28/2006 ASSET(R) Opens Boundary-Scan Technology Center in China
  2/28/2006 Intel Invests $300M for Assembly and Test in Vietnam Facility
  2/21/2006 Intel Begins Construction on Gaza IT Center
  2/21/2006 Keithley Receives Test of Time Award from Test & Measurement World Magazine
  2/16/2006 Briton EMS opts for XJTAG boundary scan to remove guesswork from test equation
  2/16/2006 Nanometrics Reports Record '05 Revenues
  2/16/2006 Spectroscope twist sees single molecules
Interviews and Forums
  2/21/2006 Agilent Technologies launches network analyzer web discussion forum
Magazine Articles
  2/16/2006 Accelerate FPGA design success with early defect discovery
  2/16/2006 Extending the reach of JTAG/Boundary Scan - PXI based Boundary Scan systems featuring advanced test resources
  2/16/2006 Measuring 3-D Semiconductor Packages
  2/16/2006 Quality metric upgrade may ease IP selection
  2/16/2006 Scopes: more than meets the eye
  2/16/2006 Signal conditioning for high-impedance sensors
Presentation and Web Seminar Archives
  2/21/2006 PXI 101: Introduction to the PXI Platform
Product Releases
  3/1/2006 Gage Applied Technologies New-Generation Digitizers Now Perform On-board Peak Detection
  2/28/2006 Portable scopes accelerate embedded-system debug
  2/28/2006 Test Probe Small Enough to Squeeze Under BGAs
  2/27/2006 Seica introduces Migration Program
  2/23/2006 Pickering Interfaces Introduces New PXI-based Battery Simulator
  2/23/2006 Rasterizers add eye and jitter measurements, ARIB support
  2/21/2006 Agilent introduces industry's fastest DRAM production tester
  2/16/2006 Agilent introduces new oscilloscope
  2/16/2006 Bluetooth testers support V2.0 + EDR
  2/16/2006 Defect Inspection and Analysis Using Atomic Force Microscopy
  2/16/2006 Espec's thermal shock chamber needs little room
  2/16/2006 Quake detector preps for market
Reports
  2/20/2006 What's Inside .. Apple iPod nano?
  2/17/2006 SEMI Book-to-Bill Ratio on the Rise
  2/16/2006 2006 Semi Market Growth to be Followed by Slowdown
  2/16/2006 Growth of European test, measurement equipment market hinges on awareness
Web postings
  2/20/2006 A Unified DFT Verification Methodology
  2/16/2006 How to Choose an OTDR to Test and Troubleshoot LAN Infrastructure
  2/16/2006 How to Select an OTDR
 
Dynamic Burn-In of High Pin Count Logic Devices with Monitoring Capability
Stephen Tsun, Sales Manager, INCAL Technology

Traditional burn-in driver electronics are not meeting the demand of ‘high pin count’ devices burn-in requirements. The increasing pin-count and more complex devices for the ‘high reliability applications such as automotive, medical ICD, and military’ require higher quantity of drive channels with monitoring capability.

Higher device pin count requires that the burn-in equipment contain a larger number of Drivers and Sensors that can be configured as driver channels, sensor channels, or channels with a dual role. The voltage ranges should be near the 0 to 5 volt range.  Memory speeds are also a factor.  With Flash you should be able to access memory at 10 MHz and with SRAM closer to 25 MHz.  Memory is allocated behind each pin so that it can drive and sense signals at higher speeds.  The greater the memory depth, the higher the test coverage you can achieve, so you should have 16 Megs behind each pin.  For certain applications you may want to have greater memory, so you should be able to cascade memory and access it serially, using some standards like Serial Vector Format (SVF) that is used in JTAG testing.

The monitoring channels should be able to record the time and date of failures for better report preparation.  The system should be able to monitor DUT outputs of either vector comparison, sign of life, frequency, or voltage.

To confront the high current and low voltage requirements of burn-in testing, Power Module should support three isolated power regulators with current as high as 30A and voltages as low as 0.5V with 12 bit precision programming.  An optional low cost Bulk Power configuration should also be available.

INCAL‘s ‘Infinity 160 Tracer® Burn-In System’ addresses many of these requirements.  A number of companies in the Medical, Military and Micro-Processor markets and many ‘test houses and laboratories’ have adopted INCAL’s ‘Infinity 160 Tracer® Burn-In System’ platforms.  See more information on this system at http://www.incal.com/isystem.htm

 
Optimize Your Burn-In Design

Randy Spivey, Randy@ceibis.com, VP Sales & Marketing, CEIBIS

In order to optimize your burn-in design a number of questions should be answered.  At CEIBIS, we use a one-page technology questionnaire in order to understand the total application in a time efficient manner. Regardless of process node, device technology, or system environment- our goal is to ensure a product with premium signal integrity and accurate power sourcing.

You should have the following information for calculating trace impedance, high speed/signal integrity design verification, and tuning/termination resistor values:

• Device VIH/VIL
• Device max/min VIN
• Device I/O IBIS model
• Clock skew tolerances
• Critical signal edge timing specification
• System frequency

The following information is requested for final test and validation.

• Junction/Ambient temperature 
• Device power supply settings 
• Estimated DUT power 
• Test patterns/vectors 
• Passive or active thermal control

One should expect, if they are dealing with a full-service burn-in board manufacturer that they will use the latest intelligent software and simulation tools to predict the performance of critical signals during the burn-in environment. The days of using a mechanical drawing software are long gone. We routinely design boards with specific rise/fall times for critical clock signals and can actually email o-scope pictures depicting the waveform of the signal including overshoot/undershoot prior to the board ever being fabricated.

Of course, not all designs are that critical and requiring of such pre-design engineering. In those cases, one should still expect that the burn-in board manufacturer that they choose will incorporate “best known” design practices gained by supporting a wide spectrum of technologies and incorporate into their burn-in board strategy at a minimum the following:

  • Routing topology that minimizes signal reflection
  • Controlled voltage drop across the board
  • Thermal budget assessment that incorporates the correct selection of material thickness and design of plane layers to insure both sufficient current carrying capability and DUT (device under test) isolation, if required

Burn-in board designs, regardless of the complexity of the device, requires a thorough understanding of the application to insure that the end-product is robust and creates a platform for a successful qualification and/or production burn-in.  Optimized burn-in board designs begin with an understanding of which questions to ask and having the right tools and the expertise to engineer the right solution.  At CEIBIS, we incorporate the use of our one-page technology questionnaire, pre-design review meeting and close interaction between our design team and the customer all contributing to an optimized burn-in board design.

 
Next Issue's Product/Service Focus
In our next issue of Product/Service Focus we will cover Inspection Equipment/Automated Optical Inspection. You can add or upgrade a listing before the next issue comes out.

If you would like to include an exclusive article on how to best select Inspection Equipment/Automated Optical Inspection, please contact LouisUngar@ieee.org.
 

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Events/Announcements
This month:
2/27 - 3/3
   Measurement Science Conference
5/7 - 5/10
   ESTECH 2006
3/2 - 3/4
   Winter Summit 2006
3/5 - 3/10
   OFC/NFOEC 2006 by the Optical Society of America
3/6 - 3/10
   Lead Free: Myths and Realities - Expanded Series
3/6 - 3/10
   Test Track at Design, Automation and Test in Europe (DATE 2006)
3/7 - 3/9
   EMV 2006
3/7 - 3/8
   MICROTECH 2006, Design, Manufacturing and Test
3/7 - 3/9
   Lean Manufacturing and Management Training Series
3/7 - 3/9
   IPC/JEDEC 12th International Conference
3/8
   Managing Noise and Ground in Precision Analog System Applications
3/21 - 3/23
   Semicon China 2006
3/26 - 3/31
   PCB Design Conference West
3/26 - 3/30
   International Reliability Physics Symposium
3/27 - 3/29
   International Symposium on Quality Electronic Design
3/28 - 3/30
   Lean Manufacturing and Management Training Series
4/3 - 4/6
   SAE 2006 World Congress
4/3 - 4/6
   IEEE Wireless Communications & Networking Conference (WCNC)
4/4 - 4/6
   Aerospace Testing Expo 2006 Europe
4/4 - 4/7
   Test & Measurement China
4/9 - 4/12
   13th International Test Synthesis Workshop
4/11 - 4/14
   Lead Free: Myths and Realities - Expanded Series
4/18 - 4/21
   IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
4/18 - 4/20
   Lean Manufacturing and Lean Management Training Series
4/20 - 4/21
   Advanced Methods for Uncertainty Estimation.. AMUEM
4/20 - 4/21
   Medical Measurement and Applications
4/24 - 4/27
   Instrumentation and Measurement Technology Conference (IMTC2006)
4/29
   International Workshop on Imaging Systems and Techniques
4/30 - 5/4
   24th IEEE VLSI TEST SYMPOSIUM (VTS 2006)
5/1 - 5/4
   Antenna Measurements Techniques Association Europe
5/1 - 5/3
   Teradyne Users Group (TUG)
5/2 - 5/4
   International Conference on Embedded Technology
5/3 - 5/4
   International Workshop on Infrastructure IP (I-IP 2006)
5/9 - 5/11
   Vision Show East 2006
5/10 - 5/12
   North Atlantic Test Workshop (NATW 2006)
5/16 - 5/19
   AUTOMOTICA
5/16 - 5/17
   Boundary Scan Days
5/16 - 5/18
   Lean Manufacturing and Management Training Series
5/21 - 5/25
   11th IEEE European Test Symposium 2006
5/30 - 6/1
   SMT/Hybrid/Packaging 2006--System Integration in Micro Electronics
6/4 - 6/8
   Globalcomm 2006
6/6 - 6/9
   Lead Free: Myths and Realities - Expanded Series
6/6 - 6/8
   Sensors Expo
6/11 - 6/16
   IEEE MTT-S/International Microwave Symposium
6/11 - 6/14
   Southwest Test Workshop (SWTW 2006)
6/13 - 6/15
   Lean Manufacturing and Management Training Series
6/21 - 6/23
   IEEE International Mixed-Signals Testing Workshop (IMSTW'06)
6/21 - 6/23
   International Mixed-Signals Testing Workshop (IMSTW'06)
7/10 - 7/14
   Semicon West 2006
7/10 - 7/12
   International On-Line Testing Symposium
7/24 - 7/28
   Design Automation Conference (DAC)
8/2 - 8/4
   Memory Technology, Design, and Testing (MTDT 2006)
8/14 - 8/18
   EMC Symposium
9/7 - 9/15
   EOS/ESD Symposium
9/18 - 9/21
   AutoTestCon 2006
9/25 - 9/28
   Assembly Technology Expo (ATExpo)
10/24 - 10/26
   International Test Conference (ITC) 2006
11/6 - 11/9
   Space Simulation Conference
11/14 - 11/16
   Aerospace Testing Expo 2006 North America
12/6 - 12/7
   IP/SOC 2006 (IP Based SoC Design) Conference
New Definitions
New terms added to the Test Definition section:
Bridge Fault
Dependent Fault
Failure Mode
False Alarm
Highly Accelerated Life Test (HALT)
Highly Accelerated Stress Screening (HASS)
Non-critical or Noncrirical Failure
Probable Fault
Race Hazard
Random Failure
Relevant (Nonrelevant) Failure
Soft Fault
Transient Failure
We now have 2136 test terms in our Test Definition section.

Share your definitions with the test community.