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Volume 11 Number 10 May 16, 2007

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This Issue's Feature Articles

Design for Boundary Scan Testability Beyond Static Connectivity Tests


Heiko Ehrenberg, Manager of US Operations, GOEPEL Electronics

Boundary Scan Skews Test Coverage Tradeoffs in your Favor

By Arden Bjerkeli, Director of Customer Application Support, 
ASSET InterTech, Inc.

Using JTAG to Preserve Board Level IP


Dominic Plunkett, Chief Technology Officer, XJTAG, Ltd.

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Product/Service Focus

This issue's focus is Boundary Scan Test
You can view and add to our existing list of Test Products/Services, Test Literature, Test Definitions, Test Vendors, containing "boundary," "scan," or "boundary scan."

What's New in Test
  5/15/2007 Dage honors Ascentek with President’s Award
  5/14/2007 Agilent Technology's profit rises
  5/14/2007 STATS ChipPAC establishes R&D center to focus on TSV, embedded die technologies
  5/11/2007 Agilent's test solution used to validate Alcatel-Lucent TPSDA
  5/11/2007 Teradyne Users Group conference draws large crowd
  5/10/2007 GOEPEL electronic exhibits revolutionary JTAG/Boundary Scan Equipment at NEPCON UK 2007
  5/9/2007 Agilent announces strategic partnership with Mentor Graphics
  5/8/2007 Teradyne completes major test system upgrade for Belgacom
  5/3/2007 TI to invest $1B in new Philippines assembly, test plant
  5/2/2007 IBM said to cut 1,315 U.S. jobs
  5/1/2007 Supreme Court hands tech firms patent victories

Come to a Three-Day Course

Random Vibration and Shock Testing, HALT, ESS, HASS

in Tinton Falls, NJ on June 12-14, 2007 

Application Notes
  5/10/2007 Amplifier cancels common-mode voltage
  5/10/2007 Microcontroller as voltmeter, testing lithium-battery chargers, canceling common-mode voltage, and more
Case Study
  5/1/2007 Check the clock oscillators
  5/1/2007 NIST issues RFID security guidelines
Interviews and Forums
  5/11/2007 What to expect at 45-nm
  5/1/2007 PXI turns 10
  5/1/2007 The hub between stimulus and test
Magazine Articles
  5/16/2007 Chipmakers urge lower ESD target levels
  5/16/2007 Test your products for PCIe
  5/1/2007 A Study of Copper Dissolution During Pb-Free PTH Rework Using a Thermally Massive Test Vehicle
  5/1/2007 Automating Software Configurations in Test Labs
  5/1/2007 Building Test Applications At the GUI Level
  5/1/2007 Defect-Detection Strategies
  5/1/2007 Implementing Change On the Test Floor
  5/1/2007 Putting Photons In Their Place - Optical Fiber Signal Switching
  5/1/2007 Spacecraft EMC PROBLEMS Part 2
  5/1/2007 Stimulating the Pulse of Today’s Electronics
Presentation and Web Seminar Archives
  5/10/2007 Measure nanoamps to ensure accurate computer clocks

Come to a Three-Day Course

Design for Testability and for Built-In Self Test

by Louis Y. Ungar in Houston, TX on June 25-27, 2007 

Product Releases
  5/16/2007 XJTAG adds support for Xilinx Virtex-5 FPGA System monitor
  5/15/2007 Portable tester identifies ONTs on FTTx F2 fibers
  5/14/2007 Google-inspired eye tracker counts every look
  5/10/2007 Signal analyzer has added measurement, security features
  5/10/2007 Zigbee software package enables low-cost, one-box testing
  5/9/2007 Willtek Communications introduces protocol analyzer for TETRA
  5/8/2007 Certess tool tests verification environments
  5/8/2007 Investigate and report test data
  5/8/2007 VI Technology Announces Release of Arendar 2007
  5/7/2007 All-band tester monitors optical components
  5/7/2007 Rohde & Schwarz expands MPEG-2 measurement platform
  5/3/2007 AC/DC current probes employ hybrid tech
  5/3/2007 IBM touts chips made with self-assembly nanotechnology
  5/3/2007 Rohde & Schwarz showcases solutions for automotive production
  5/2/2007 New XiDAT 2.0 With 2M Pixel Imaging System From Dage
  5/1/2007 Agilent Technologies Introduces Fixed, Mobile WiMAX Manufacturing Test for Consumer Premises Equipment
  5/1/2007 Memory Fault Detection IP Meets International Safety-Critical Standards
  5/1/2007 Not your average power analyzer, dc unit makes short work of tedious test setups
  5/1/2007 Pickering Interfaces introduces an LXI Remote AC Power Management Switch
  5/8/2007 Worldwide MEMS Systems Market Expected To Reach $95 Billion By 2010
  5/7/2007 Eastern Europe is ‘electronics hotbed’
  5/5/2007 Fix It Or Nix It?
  5/4/2007 Automotive sensor market to grow $17B by 2013
  5/1/2007 US Department of Justice will not oppose IEEE patent policy
Web postings
  5/8/2007 Nuke detectors could eventually reside in your cellphone
  5/1/2007 Design-for-Test Tool Would Ensure Maximum Benefit from JTAG
  5/1/2007 Managing Testability - With Tools or Without
Design for Boundary Scan Testability Beyond Static Connectivity Tests
Heiko Ehrenberg, Manager, US Operations, GOEPEL Electronics

IEEE Std. 1149.1 defines test resources that are implemented into digital integrated circuits and used primarily to verify board level pin connectivity. The underlying principle of serially transmitting the test vectors, however, limits the frequency with which Boundary Scan I/O pins actually toggle to the kilohertz range. This means that dynamic connectivity problems (such as "cold" solder joints) cannot be detected in most instances, and that AC coupled, high-speed networks cannot be tested at all (for the latter, IEEE 1149.6 has been developed to come to the rescue). Furthermore, on most Units Under Test (UUT) the number of Boundary Scan enabled devices is limited. For example, most memory devices do not provide IEEE 1149.1 capabilities. Simple logic gates, low-pin count devices (such as serial interface controllers), and mixed signal components, such as analog-to-digital and digital-to-analog converters ( ADC/DAC) typically do not implement Boundary Scan either. A good portion on almost all UUTs consists of just such devices. Some of these devices can be included in so-called Boundary Scan Cluster tests, but how do we measure their testability? And how can we account for design for testability requirements for such non-Boundary Scan circuits?

Frequently, Boundary Scan Cluster Tests for mixed signal circuitry are not automatically generated but rather written manually by a test engineer. This means that the test engineer also needs to analyze the test coverage such tests contribute to the overall test coverage for the Unit Under Test. For example, an Extended Boundary Scan test for a DAC may verify the connectivity on the digital input pins and the analog output(s) as well as the converter functionality. Such a test application would require access to the analog output pins with test resources the Boundary Scan tool can control, such as a mixed-signal I/O module. The test pattern would include digital stimuli that result in deterministic voltage levels on the DAC outputs if the device under test functions properly and its pin connections are free of any defects. The testability of non-Boundary Scan circuitry such as this DAC heavily depends on access to the control signals of the device under test. Cluster Test applications utilizing Boundary Scan resources need to be considered during board design to ensure that the pins of non-Boundary Scan devices to be tested can be accessed from Boundary Scan resources or external tester resources. Interface clusters (such as RS232, USB, Ethernet, CAN, and other bus interfaces) may especially require dynamic stimulus of a minimum frequency. During design reviews, both test engineers and designers need to analyze such circuit clusters and identify the test resources needed to achieve the desired test coverage. The chosen strategy may combine Boundary Scan access on the UUT with Functional Test resources where Boundary Scan provides simple access to the digital circuit nodes while Functional Test equipment supports analog and dynamic stimulus and measurements.

There is no standardized way to analyze testability or to measure test coverage in the industry. For Boundary Scan connectivity tests, the test coverage for stuck-at faults, opens, and shorts can be calculated based on the automatically generated test programs. Often times, these test programs cover more than just Boundary Scan I/O pins, though. Devices such as buffers and serial resistors need to be included in the test coverage statistics. Boundary Scan test pattern can only verify the existence of a serial resistor, not its value, though. Hence, the resistor cannot be considered fully tested for all its properties. Cluster Tests contribute to test coverage on non-Boundary Scan devices that needs to be accounted for as well. There are several attempts in the industry to introduce common metrics for test coverage that are independent of the test technology used and instead consider the properties of the device pins and connections on the UUT. Refer to International Test Conference (ITC) proceedings of the previous years for details.

Boundary Scan Skews Test Coverage Tradeoffs in your Favor

Arden Bjerkeli, Director of Customer Application Support, 
ASSET InterTech, Inc.

In striving for high-level test coverage in a PCA (printed circuit assembly) factory, it seems most decisions involve tradeoffs. One of the most obvious is test coverage vs. test cost.  Diminishing returns on the test coverage effort eventually give way to the escalating cost to achieve the incremental coverage.  Through optimization of your test strategy, you can lower your test cost, making headroom for higher coverage.

In the end, the real objective becomes the optimum test plan for a PCA. And that optimum plan would feature the highest test coverage achievable within your cost target.  The addition of boundary scan to your test strategy can pull your cost down and raise your test coverage, significantly shifting the point at which test cost will outweigh the need for higher quality.

There are other tradeoffs involved in test plan development. Obviously, the reasons test engineers strive for full test coverage include better manufacturing yields, better quality end products, fewer product returns, competitive advantages in the marketplace and others. But, there are a myriad of reasons – some technical and others financial – why test plans settle for less than full test coverage. This means that the benefits of full test coverage are being traded for some other factor, technical, financial or otherwise.  

Optimum vs. Full Test Coverage

No single test technology is capable of providing full test coverage. This realization has led to the development of a wide variety of techniques for testing PCAs.  The challenge for a test strategist is to find a combination of test technologies that result in the most effective test plan, considering not only cost and coverage, but also life-cycle volume, production rate, the product’s design-for–testability features and other factors.

Broadly speaking, test is usually divided into structural or assembly test and functional or system test. Some of the prevalent test technologies can be applied in both areas while others can not. The typical structural test technologies that are most often considered include boundary scan (JTAG or IEEE 1149.1), automated optical inspection (AOI), automated x-ray inspection (AXI), manual visual inspection, in-circuit testers (ICT), manufacturing defect analyzers (MDA) and flying probe testers (FPT). In functional test some of these test technologies are employed in tandem with different test methodologies like system mock-ups, emulation, simulation, self-diagnostics, instrumentation, test executives, rack-and-stack and others.  A successful test strategy will employ a combination of several of these technologies

Each of these test technologies and test techniques has its own pro’s and con’s, but since this newsletter is focused on boundary scan, the remainder of this column will focus on how boundary scan can help test engineers achieve optimum test coverage.

Driven by the increasing density of PCAs and the resulting loss of physical access for test probes, boundary scan/JTAG was developed as an access-free test technology. JTAG stimulates and monitors on-board nets and connections via registers in the I/O of digital chips. An external tester controls these registers and analyzes responses by serially shifting test vectors via a JTAG serial bus. Some of the many benefits of JTAG which can optimize test coverage are the following:

1        Non-invasive. No fixtures, no stress on PCA, no test points needed for signal nets.

2        Very high structural test coverage around JTAG devices.

3        Device identity provided by reading embedded registers.

4        Relatively inexpensive.

5        High test development automation.

6        Effective diagnostics to resolve shorts and opens.

7        On-board programming of flash and configuring of CPLDs and FPGAs.

Planning Test Coverage

If test coverage is neglected early on, inadequate test coverage will doggedly follow a product throughout its lifecyle, increasing costs in manufacturing, continuing engineering, support and post-sales warranty returns. Acceptable test coverage doesn’t just happen; it must be planned. 

An optimized test plan will take advantage of the complementary coverage capabilities of several test technologies, such as JTAG, visual inspection and ICT. With several technologies included in the plan, the total time-to-test for a product can be distributed over several stations in the manufacturing production line so that no one point restricts the flow of the line. In addition, test planners need not strive for the maximum test coverage that each test technology can provide. Maximizing test coverage for each technology would cause numerous test redundancies throughout the manufacturing process. Shifting some test coverage to JTAG would reduce overall test and manufacturing costs by eliminating test points. This in itself would reduce layout space requirements, reduce fixture procurement costs, reduce fixture maintenance costs and reduce the test load on ICT systems, providing headroom for the unexpected contingency. 

Each test technology in the test plan should play to its strength. JTAG test, for instance, is very good at detecting, isolating and diagnosing shorts and opens, as well as performing on-board programming. But boundary scan may not offer adequate coverage where analog devices dominate a section of the PCA. In this case, test points could be designed into the PCA so ICT could complement the design’s JTAG test coverage by providing coverage in the analog partition of the design.

Learn More About Test Coverage

This discussion only scratches the surface of test coverage. If you’d like to learn more about this critical topic, attend a free one-hour webinar on May 23, 2007, at 11:30 EST. Go to the ASSET InterTech web site at for more details and to register.

Using JTAG to Preserve Board Level IP

Dominic Plunkett, Chief Technology Officer, XJTAG, Ltd.


The complexity and programmability of modern embedded boards means that knowledge built up during debugging and testing must be regarded as Intellectual Property (IP) and therefore preserved. But many of the processes and tools used today do not provide a means to preserve or pass on this IP, and thereby forego valuable opportunities to save time and improve quality during subsequent stages of product development.

Boundary scan testing creates a test infrastructure that is inherently suited to preserving and re-using test knowledge throughout the product lifecycle. It provides a convenient means for original equipment manufacturers, design houses, test specialists and electronic manufacturing services ( EMS ) providers to maximize the value of this test IP, which is every bit as valuable as design IP as it can be reused, enhanced, and extended, to add value throughout the product lifecycle.

Preserve Test Knowledge as IP

Test engineering often happens at least twice in a product's lifetime. The first time is during prototyping, as development engineers create their own tests as part of the design and debugging phase. However, many of the tools and techniques used in development laboratories do not provide an intuitive or standardized way to record the tests or the results. As a result, this board-level test IP, built up during development, is mostly wasted as production test engineers are effectively forced to carry out a second test engineering project for the same product.

XJTAG’s Boundary Scan - a Natural Test IP Framework

Embedding a boundary scan chain on the board to interconnect the test ports of JTAG-compliant components creates the foundation for product teams to create valuable IP by recording test knowledge. The XJTAG system combines the BSDL files for the components on the board with the board netlist and a test script written by the engineer that describes how the device is to be tested. The XJTAG scripts (see example) are written in an intuitive high level language, which is easily readable by electronic designers and software engineers.

The use of a high level language abstracts engineers from the intricacies of the boundary scan data stream. This supports fast test development, eliminates human error, and facilitates development of sophisticated test routines that require minimal physical access to the board.

Device-Centric Scripts Promote Re-Use

The device-centric nature of XJTAG tests means that a script for a particular device can be stored and re-used at a later date when the same component is designed into a subsequent product. In this way, XJTAG achieves a device-centric approach to boundary scan testing that facilitates re-use of test knowledge acquired throughout the product lifecycle. Hence, engineers using this technique are effectively creating test IP that can be used again and again to reduce development costs and turnaround time for a multitude of board and product designs.

The script-based nature of the test allows easy integration with other production test techniques such as ICT, flying probe or functional testing. This provides additional freedom for test engineers to create hybrid test strategies that take advantage of all the physical and electrical characteristics of the board, and thereby achieve very high levels of test coverage.


Great power is gained from the seamless flow of test information from one department to the next, continuously growing and being reused. The key to exploiting this power is to understand the value of test knowledge as precious IP, and to take steps to preserve it.

The JTAG test structure provides a standard platform which can be utilised throughout a given product’s complete lifecycle. Furthermore, focusing test compilation at the device level, rather than the board level, maximises the value of re-use by allowing proven test scripts to be incorporated directly in subsequent projects.  

XJTAG offers a FREE 30-day evaluation period, so you can try the XJTAG Development System before you buy: apply here.


Next Issue's Product/Service Focus
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6/12 - 6/14
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
6/25 - 6/27
   Design for Testability and for Built-in Self Test
   Cost Effective Tests Using ATE, DFT and BIST
9/17 - 9/21
   AutoTestCon 2007
5/14 - 5/17
   International Electrostatic Discharge Workshop
5/15 - 5/17
5/20 - 5/24
   12th IEEE European Test Symposium (ETS'07)
5/23 - 5/24
   International Workshop on Silicon Debug and Diagnosis (SDD07)
   Maximizing Test Coverage
5/24 - 5/25
   European Board Test Workshop (EBTW)
5/31 - 6/1
   Defect and Fault Tolerant Nanoscale Architectures (NANOARCH 07)
6/3 - 6/8
   IEEE MTT-S/International Microwave Symposium
6/3 - 6/6
   Semiconductor Wafer Test Workshop (SWTW 2007)
6/4 - 6/8
   44th Design Automation Conference
   Agilent Technologies Showcases New Medalist x6000 Automated X-ray Inspection System
6/11 - 6/13
   Sensors Expo & Conference
6/18 - 6/21
   International Metrology Congress
6/18 - 6/20
   International Mixed-Signals Testing Workshop (IMSTW'07)
6/18 - 6/20
   International GHz/Gbps Test Workshop (GTW 07)
6/19 - 6/22
   Nepcon Malaysia
6/19 - 6/21
   LXI Consortium General Meeting
6/20 - 6/21
   Successful Lead-Free RoHS Strategies Conference – Do it Right, Do it Now
6/20 - 6/22
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
6/21 - 6/24
   Nepcon Thailand
6/27 - 6/28
   High Frequency Measurements Course
7/8 - 7/13
   EMC Symposium
7/9 - 7/11
   International On-Line Testing Symposium (IOLTS'07)
7/10 - 7/12
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
7/16 - 7/20
   Coordinate Metrology Systems Conference (CMSC)
8/7 - 8/9
   National Instruments' NI Week
8/21 - 8/23
   International Military & Aerospace / Avionics COTS Conference
8/28 - 8/31
   NEPCON South China
9/9 - 9/12
   International KGD (Known Good Die) Packaging & Test Workshop
9/12 - 9/14
   VII SEMETRO - 7th International Seminar on Electrical Metrology
9/19 - 9/21
   International Exhibition on Test Equipment 2007
9/19 - 9/21
   IPC Executive Market & Technology Forum
9/21 - 9/23
   IEEE Wireless Communications, Networking and Mobile Computing (WiCOM2007)
9/26 - 9/28
   International Symposium on Integrated Circuits
9/26 - 9/28
   International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)
9/26 - 9/28
   IPC Midwest Conference & Exhibition
10/7 - 10/11
   SMTA International 2007
10/9 - 10/11
   LXI PlugFest and General Meeting
10/9 - 10/11
   Asian Test Symposium (ATS’07)
10/10 - 10/12
   IPC Executive Market & Technology Forum
10/11 - 10/13
   Workshop on RTL and High Level Testing
10/22 - 10/24
   IPC Executive Market & Technology Forum
10/22 - 10/23
   IEEE Product Safety Engineering Society Symposium
10/23 - 10/25
   International Test Conference 2007
10/24 - 10/26
   Automotive Testing Expo North America
10/30 - 10/31
   NEPCON East
11/4 - 11/9
   Antenna Measurement Techniques Association (AMTA) Symposium
11/6 - 11/8
   Aerospace Testing Expo 2007 - North America
11/6 - 11/8
   Bohai Electronics Week
11/6 - 11/8
11/11 - 11/13
   National Quality Education Conference
11/13 - 11/16
11/27 - 11/28
   TestForum 2007
12/5 - 12/6
   IP Based SoC Design Conference & Exhibition
New Definitions
New terms added to the Test Definition section:
Amplitude Shift Keying
Arbitrary Function Generator
Complementary Output
Continuous Mode
DC Accuracy
Delayed Non-Return-to-Zero
Differential Output
Digital Pattern
Digital Waveform Generator
Direct Digital Synthesizer
Formal Verification
Frequency Sweep
Functional Verification
Hypothesis Testing
Inter-symbol Interference
Logic Simulation
Margin Testing
Mutation Analysis
Nondeterministic Polynomial-time hard
Phase-Shift Keying
Pseudo Random Binary Sequence
Pseudo-random Word Stream
Pulse-Width Modulation
Rectangular Wave
Serial Peripheral Interface Bus
Spurious Free Dynamic Range
Statistical Error
Systematic Error
Through Silicon Via
Type I Error
Type II Error
We now have 2491 test terms in our Test Definition section.

Share your definitions with the test community.