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An A.T.E. Solutions, Inc. Internet Publication
Volume 11 Number 9 May 1, 2007
 


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This Issue's Feature Articles

Design-for-Test Tool Would Ensure Maximum Benefit from JTAG

By Dave Bonnett, Technical Marketing Manager, ASSET Intertech, Inc.

Managing Testability - With Tools or Without

By Louis Y. Ungar, President, A.T.E. Solutions, Inc.

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Product/Service Focus

This issue's focus is Design for Testability Tools
You can view and add to our existing list of Test Products/Services, Test Literature, Test Definitions, Test Vendors, containing "environmental"

What's New in Test
Announcements
  4/26/2007 Dage Wins Two Industry Awards For Its XD7600NT
  4/26/2007 KLA-Tencor 3Q profit jumps 60 percent
  4/26/2007 National Instruments Reports Quarterly Revenue of $172 Million
  4/24/2007 LogicVision Reports First Quarter 2007 Financial Results
  4/23/2007 House subcommittee approves bill to double funding for NIST programs
  4/19/2007 Bill Gates sees tech revolution without limits
  4/19/2007 Qimonda, Advantest team on GDDR5 testing
  4/19/2007 Teradyne announces Q1 results
  4/18/2007 Agilent Technologies Wins Prestigious EDN Award for Medalist Bead Probe Technology
  4/18/2007 Agilent wins Supply-Chain Excellence Award
  4/16/2007 Dage announces Hitech as new Brazil sales representative

Come to a Three-Day Course

Design for Testability and for Built-In Self Test

by Louis Y. Ungar in Houston, TX on June 25-27, 2007 

Course Description
  4/26/2007 A.T.E Solutions announces design course
Magazine Articles
  4/30/2007 We Need a New Approach to Accurately Simulate Large Circuits
  4/26/2007 Measuring nanoamperes
  4/25/2007 Needed: New Thinking For Wireless/RF Testing
Blogs
  4/19/2007 What is a femtometer?
Presentations and Web Seminar Archives

Come to a Three-Day Course

Random Vibration and Shock Testing, HALT, ESS, HASS

in Tinton Falls, NJ on June 12-14, 2007 

Product Releases
  4/30/2007 LabVIEW SignalExpress simplifies data logging, instrument control
  4/30/2007 MEMS RF Switch Operates To 26 GHz
  4/27/2007 Metering IC features embedded flash memory
  4/26/2007 GOEPEL electronic introduces new AOI System with Extended Colour Technology
  4/23/2007 Agilent Claims to Have Launched World's Fastest 3D In-Line Automated X-Ray Inspection
  4/23/2007 Agilent Technologies Introduces Low-Cost In-Circuit Test
  4/23/2007 Phoenix|x-ray announces introduction of new high-res CT system
  4/20/2007 FocalSpot Releases Verifier Plus X-Ray Inspection System
  4/20/2007 Network analyzer has four-port architecture
  4/18/2007 Pickering Interfaces expands line of PXI switch modules
  4/18/2007 Precision DMM Opens Eyes With 14 Special Measurement And Display Features
  4/18/2007 Rohde & Schwarz instruments gain LTE options
  4/17/2007 Agilent Technologies Reduces Endurance Test Time for Non-Volatile Memory Cells
  4/17/2007 Keithley ACS enhances semiconductor characterization
  4/17/2007 Mentor revamps hardware-assisted verification offering
  4/17/2007 Vicor announces high-density bus converter
  4/16/2007 Equivalence checker supports FPGA optimizations
  4/16/2007 National Instruments LabVIEW 8.2.1 Provides Support for Windows Vista
  4/16/2007 Sensor signal conditioning packages eliminate aliasing
  4/16/2007 Slaughter packs six functions into one electrical safety tester
Reports
  4/26/2007 U.S. high-tech industry posts second year of job growth in 2006
  4/20/2007 Gartner predicts semi equipment spending to rebound in 2008
Web Postings
  4/30/2007 Post AOI, X-ray or In-Line Test Handling Considerations
  4/26/2007 Diagnostic testing (and tasting?)
  4/16/2007 Environmental Test Using MIL-STD-810
 
Design-for-Test Tool Would Ensure Maximum Benefit from JTAG

By Dave Bonnett, Technical Marketing Manager, ASSET Intertech, Inc.

The importance of properly designing boundary-scan (JTAG) test capabilities into a printed circuit board is critical to achieving maximum test coverage.

If JTAG test is not properly designed into a board, JTAG test coverage will almost certainly be diminished, product development schedules could be delayed by the need to develop alternative test strategies and production ramp-up would be postponed. In other words, bad boundary-scan DFT inevitably decreases the quality of the product and increases its opportunity costs for the manufacturer. A product that’s late to market means missed sales opportunities that will probably never be recovered.

A JTAG DFT tool would ensure an accelerated time-to-market for many new product designs by streamlining and improving the reliability of the manual testability analyses that are typically produced today. Instead of a testability analysis taking approximately three weeks for an engineer to compile, a boundary-scan DFT tool could produce a testability analysis in a matter of hours.

In addition, a DFT tool could eliminate time-consuming re-spins of a design or design work-arounds that must be developed to compensate for low testability. Unacceptably low testability often isn’t discovered until prototypes are built and test routines fail to function as expected. A DFT tool could discover DFT flaws in the design before first prototypes are built. Test deficiencies could be addressed and flaws corrected before prototypes are produced, ensuring first prototypes will be usable and production ramp-up can proceed in a timely fashion.

Automating Boundary-Scan DFT

There are usually two basic reasons why boundary-scan test capabilities are not properly designed into a product. First, the engineers who make up the design team may not be familiar with JTAG and how to design a fully-functional boundary-scan infrastructure into a circuit board. And second, the likelihood of human error during a manual testability analysis can be high, especially when engineers must analyze a hardcopy schematic that sometimes stretches to hundreds of pages.

Citing examples of each of these cases is perhaps the most effective way to understand their implications.

A recent testability analysis performed by ASSET’s engineers revealed that the integrity of JTAG signals on a circuit board was diminished because of other on-board signals. It turned out that the design team had overlaid the boundary-scan signals on the same net that carried SPI signals. The two sets of signals were interfering with each other, limiting the amount of JTAG test coverage available on the design. In this case a lack of experience or knowledge of JTAG resulted in poor boundary-scan DFT.

In other cases, we have seen how simple mistakes can have disastrous effects on JTAG test coverage. For example, the wrong pins on a device can be connected and this will create a break in the scan chain. In one instance of this, the wrong pin on a field programmable gate array (FPGA) was designated as the JTAG test-data-in (TDI) pin for the device. We’ve also seen instances where the JTAG test-mode-select (TMS) and test clock (TCK) pins on a device were mistakenly swapped. It is difficult for an engineer to detect these kinds of mistakes during a manual testability review of a lengthy hardcopy schematic.

Functionality of a JTAG DFT Tool

By including the functionality described below, a boundary-scan DFT tool could eliminate design errors and ensure that acceptable design practices are followed.

1. Applying an Expert Knowledge Base

Early in design before schematics are available, a JTAG DFT expert knowledge base could form the basis for posing interactive queries to the design team. In this way, the DFT tool would discover whether standard JTAG design practices were followed. The tool could guide the design team through a set of JTAG testability requirements and specification definitions. This type of process would help establish and enforce corporate standards for testability at the very earliest stages of design.

2. Rules-Based Design Analysis

Later, when schematics are available, a JTAG DFT tool could automatically analyze the design based on a DFT rules-based engine. The rules engine would verify when a rule is followed and alert designers when a rule is broken. This step avoids re-spins of prototype designs to insert additional JTAG testability and it maximizes JTAG test coverage.

3. Automating Test Coverage Analysis

A boundary-scan DFT tool which automatically performs a test coverage analysis will help engineers determine the most effective test strategy early in the design process. The objective of every test strategy is to achieve as much test coverage as possible with the lowest cost test methods. Changes uncovered by a JTAG DFT tool early in design can increase the amount of low-cost JTAG test coverage available on a circuit board and reduce the test strategy’s reliance on more expensive test technologies.

4. Reducing ICT Test

Increasing the amount of boundary-scan test coverage can reduce the need for extensive and more expensive in-circuit test (ICT). Test points can be removed from the design, ICT fixture costs can be reduced, and ICT test procedures can be simplified and accelerated during production.

5. Getting a Head Start on Boundary Scan Tests

The output from a JTAG DFT tool could be sent directly to a boundary-scan test generation tool where a JTAG test suite could be automatically produced. This would provide the design debug and manufacturing test teams the boundary scan tests they need to perform their responsibilities. Boundary-scan tests would be available to debug first prototypes and they could be re-used in field service and support applications.

In summary, we can conclude that a boundary-scan DFT tool brings many benefits to the design process, not the least of which is an accelerated time-to-market. Moreover, these benefits follow a new product as it migrates into volume production and is deployed in the marketplace.

Managing Testability - With Tools or Without

 By Louis Y. Ungar, President, A.T.E. Solutions, Inc.

There are differences of opinion on what types of automated tools should be used to achieve Design for Testability (DFT).  There are a myriad of choices. Your first consideration would be whether you want DFT for ICs, boards or systems. 

  • For ICs you would find the tool within engineering design automation (EDA) software. 

  • For boards, almost all the automated tools are boundary scan centric and at a minimum will simulate the boundary scan features of the printed circuit board (PCB).  Though intended for test program development, some have been used to “simulate” the testability (more the boundary scanability) of circuit boards. 

  • For systems, testability tools emphasize diagnostics.  Integrated Diagnostic tools exist with various levels of automation.  In each of these cases the automated tool is best if it is used by a knowledgeable testability engineer – and in some cases we have to wonder whether the tool is helping the testability engineer, or the other way around.

Testability FOR Designers  

Perhaps we need to back up to the reason why we have these tools.  They are intended to make it simpler for the designer to create circuits, which can be readily tested.  The tool should be intended for use by a designer who not only has to contend with the set of guidelines but also to understand the reasons.  Alternatively, the designer could just let the tool take over his/her design and let the design transform to a testable one.  Most designers I know have a difficult time letting anyone alter the design, human or machine, without a good reason that he/she understands.  A DFT tool cannot ignore the high resistance by designers to use them.  To overcome this resistance, the tool must explain the rationale for the testability guidelines.  Even the greatest tool is worthless if it is not used. 

Testability FOR Managers

During a panel I led at AutoTestCon 2006, a number of testability tool makers presented “state-of-the-art” methodologies in design for testability.  Much progress has been made in IC-level, board-level and system-level testability tools and yet the audience was frustrated by the lack of testability experienced in their companies and organizations.  The questions raised to the presenters and the discussions that followed clearly placed the responsibility on a lack of management support for DFT.  If designers are resistant to testability, management needs to step in and at a minimum explain its benefits.  In many organizations managers do not understand or are not convinced of the benefits of DFT – or at least not enough to impose it on designers.  They look to tools to do that for them.  This rarely works, because as we said earlier, designers do not blindly follow the dictates of the tools – yet they are not well informed about the rationale behind them.

So What is a DFT Tool Supposed to Do?

Obviously, a DFT tool must assist the designer (or testability engineer) to implement important testability guidelines.  (See Design-for-Test Tool Would Ensure Maximum Benefit from JTAG  in this issue for the technical details of a JTAG DFT.)  A DFT tool, apparently also has to act as a tutorial for designers and provide some measure of importance to each guideline.  It must also acts as a management tool when a trade-off needs to be made between testability and other requirements that may conflict.

The Testability Director from A.T.E. Solutions, Inc. is such a tool.  It is a low-price software, housed in a spreadsheet template, which guides in the development of testable designs.  It contains the Inherent Testability Checklist used with MIL-STD-2165, the U.S. Government's Testability Program for Electronic Systems and Equipments, but it adds hundreds of guidelines from IC design through board and system testing.  It includes guidelines for X-ray and Automated Optical Inspection.   It also includes fixturing guidelines for bed-of nails, flying probe and even vectorless test approaches.   For each criterion, an explanation is provided so designers understand the intent of the guideline. 

The Testability Director also assists managers by having each guideline weighted in relative importance.  When a conflict arises with other design criteria, the weights can be a determining factor.  Managers also learn the benefits of individual guidelines rather than have to be put into a position of choosing between design criteria and testability criteria.  Designers are also helped by being informed of various methods to implement a testability guideline.

Do DFT Tools have to be Automatic?

Unlike other, more expensive tools – The Testability Director is not strictly automatic.  The computer processes only the ranking, weighting and scoring of the testability achieved.  Designers have to manually apply the techniques to appropriate parts of their designs.  Does that disqualify it as a DFT tool?  We don't think so.  Since designers are the ones who use the DFT tools at the urging of managers, they have to understand clearly what the tool intends for them to do.  During the process, they learn the techniques that will help them on the next design.  Test engineers, who initially assign the weights to each guideline, are also involved in the process.

What we find most valuable about the tool is that it has accomplished what none of the other tools have. Tthey create a dialog between design engineers who make their designs testable and the test engineers who benefit from it. 

The Testability Director may not be the only tool that designers would use.  DFT within EDAs, boundary-scan assessment tools, and integrated diagnostic tools are each useful aids to the designer, but without basic understanding for the goals they try to achieve, they may be just taking up storage on designers' computers, while test engineers continue being frustrated.

As a note of optimism:  At AutoTestCon 2007 the Design for Testability Panel will focus on Managing Testability.  We hope to see you there in Baltimore in September.  Alternatively email me your view on the subject.

 
Next Issue's Product/Service Focus
In our next issue of Product/Service Focus we will cover Testability and Built-In Test Products/Servic/Boundary-Scan Test. You can add or upgrade a listing before the next issue comes out.

If you would like to include an exclusive article on how to best select Testability and Built-In Test Products/Servic/Boundary-Scan Test, please contact LouisUngar@ieee.org.
 

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Events/Announcements

2007

6/12 - 6/14
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
6/25 - 6/27
   Design for Testability and for Built-in Self Test
8/6
   Cost Effective Tests Using ATE, DFT and BIST
9/17 - 9/21
   AutoTestCon 2007
4/29 - 5/2
   ESTECH 2007
4/30 - 5/3
   International Instrumentation Symposium
5/1 - 5/3
   Instrumentation and Measurement Technology Conference (IMTC)
5/6 - 5/10
   IEEE VLSI TEST SYMPOSIUM (VTS 2007)
5/8 - 5/10
   Automotive Testing Expo Europe
5/8
   Automated Test Summit 07
5/10 - 5/11
   IEEE International Workshop on Open Source Test Technology Tools
5/13 - 5/16
   IEEE Workshop on Signal Propagation on Interconnects
5/14 - 5/17
   International Electrostatic Discharge Workshop
5/15 - 5/17
   NEPCON UK
5/16
   Lead Free Workshop Featuring Dr. Jennie Hwang
5/20 - 5/24
   12th IEEE European Test Symposium (ETS'07)
5/23 - 5/24
   International Workshop on Silicon Debug and Diagnosis (SDD07)
5/23
   Maximizing Test Coverage
5/24 - 5/25
   European Board Test Workshop (EBTW)
5/31 - 6/1
   Defect and Fault Tolerant Nanoscale Architectures (NANOARCH 07)
6/3 - 6/8
   IEEE MTT-S/International Microwave Symposium
6/3 - 6/6
   Semiconductor Wafer Test Workshop (SWTW 2007)
6/4 - 6/8
   44th Design Automation Conference
6/11 - 6/13
   Sensors Expo & Conference
6/18 - 6/20
   International GHz/Gbps Test Workshop (GTW 07)
6/18 - 6/21
   International Metrology Congress
6/18 - 6/20
   International Mixed-Signals Testing Workshop (IMSTW'07)
6/19 - 6/22
   Nepcon Malaysia
6/19 - 6/21
   LXI Consortium General Meeting
6/20 - 6/21
   Successful Lead-Free RoHS Strategies Conference – Do it Right, Do it Now
6/20 - 6/22
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
6/21 - 6/24
   Nepcon Thailand
6/27 - 6/28
   High Frequency Measurements Course
7/8 - 7/13
   EMC Symposium
7/9 - 7/11
   International On-Line Testing Symposium (IOLTS'07)
7/10 - 7/12
   Fundamentals of Random Vibration and Shock Testing, HALT, ESS, HASS
7/16 - 7/20
   Coordinate Metrology Systems Conference (CMSC)
8/7 - 8/9
   National Instruments' NI Week
8/21 - 8/23
   International Military & Aerospace / Avionics COTS Conference
8/28 - 8/31
   NEPCON South China
9/9 - 9/12
   International KGD (Known Good Die) Packaging & Test Workshop
9/19 - 9/21
   International Exhibition on Test Equipment 2007
9/19 - 9/21
   IPC Executive Market & Technology Forum
9/21 - 9/23
   IEEE Wireless Communications, Networking and Mobile Computing (WiCOM2007)
9/26 - 9/28
   International Symposium on Integrated Circuits
9/26 - 9/28
   International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)
10/7 - 10/11
   SMTA International 2007
10/9 - 10/11
   LXI PlugFest and General Meeting
10/9 - 10/11
   Asian Test Symposium (ATS’07)
10/10 - 10/12
   IPC Executive Market & Technology Forum
10/11 - 10/13
   Workshop on RTL and High Level Testing
10/22 - 10/24
   IPC Executive Market & Technology Forum
10/22 - 10/23
   IEEE Product Safety Engineering Society Symposium
10/23 - 10/25
   International Test Conference 2007
10/24 - 10/26
   Automotive Testing Expo North America
10/30 - 10/31
   NEPCON East
11/4 - 11/9
   Antenna Measurement Techniques Association (AMTA) Symposium
11/6 - 11/8
   Aerospace Testing Expo 2007 - North America
11/6 - 11/8
   Bohai Electronics Week
11/6 - 11/8
   Vision
11/11 - 11/13
   National Quality Education Conference
11/13 - 11/16
   Productronica
11/27 - 11/28
   TestForum 2007
12/5 - 12/6
   IP Based SoC Design Conference & Exhibition
2/19 - 2/21
   Printed Circuits Expo®, APEX® and the Designers Summit Conference
New Definitions
New terms added to the Test Definition section:
Serial Peripheral Interface Bus
We now have 2458 test terms in our Test Definition section.

Share your definitions with the test community.