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An A.T.E. Solutions, Inc. Internet Publication
Volume 10 Number 19 October 16, 2006

International Test Conference
October 24-26, 2006

The Testability Director Version 3.2



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This Issue's Feature Articles

How to Select a Tool for Testability Analysis and Scan Insertion


Rick Fisette, Technical Marketing Engineer, 
Mentor Graphics
Product/Service Focus

This issue's focus is Scan Insertion Tools
You can view and add to our existing list of Test Products/Services, Test Literature, Test Definitions, Test Vendors, containing "Scan"

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How to Select a Tool for Testability Analysis and Scan Insertion
Rick Fisette, Technical Marketing Engineer, Mentor Graphics Design-For-Test

Effective Design For Test (DFT) is based on controllability and observability.  You need control to stimulate a fault and then propagate the effect to an observe point.  Scan is an extremely effective DFT technique which transforms all register elements into control and observe points.  Evaluating a scan insertion tool’s capabilities should consider how well the following tasks are handled: Testability Analysis, DRC Debugging, Test Logic Insertion, Scan Cell Insertion, Scan Chain Stitching.

Testability Analysis – The most valuable capability of any scan insertion tool is the testability analysis which requires comprehensive Design Rule Checks (DRCs).  Satisfying the DRCs means that once scan is inserted, the Automatic Test Pattern Generation (ATPG) tool will be able to generate patterns that achieve high test coverage.  DRCs will check that scannable registers can be controlled, clocks can capture data, scan chains can trace properly, data is stable and RAMs can be controlled.  There are many more additional categories of DRCs that should be run but are too numerous to list.  The scan insertion tool should be checking for the same things that the ATPG tool does.

DRC Debugging – After flagging all the DRC issues it will be necessary to debug those issues and identify how to fix them.  The tool should support users who prefer command line mode interaction as well as GUI users.  A really good graphical debug environment though is a powerful and intuitive tool that all users, regardless of preference, can benefit from.  Figure 1 is an example of a comprehensive debug environment.  

Figure 1 – Graphical Debug Environment for Analyzing and Resolving DRC Issues (Click to view article with figure)

The debug environment should be able to display the details of the DRC failures in a number of ways.  It combines messaging (Figure 2), schematic views and simulated values (Figure 3) with a simple way to trace through the design to track down the source of the DRC violation.  Debugging some issues is made quite a bit easier by viewing simulation results as waveforms (Figure 4).  The ability to easily browse the design hierarchy provides a quick way to identify problem areas in a design (Figure 5).  Cross selection of items from one view to another pulls the whole environment together as a comprehensive solution.


Figure 2 – Transcript view of DRCs (Click to view article with figure)

Figure 3 – Tracing simulation values with schematic view (Click to view article with figure)

Figure 4 – Waveform view (Click to view article with figure)

Figure 5 - Browse the design hierarchy (Click to view article with figure)

Test Logic Insertion – Some designs require gate level changes to address DRC issues.  Some simple testability issues such as an uncontrollable reset signal could make the design untestable.  For these reasons the scan insertion tool should be able to automatically insert logic gates to address all DRC issues.  

Scan Cell Insertion – The actual insertion of a scan cell in the design is probably the easiest step in the whole process.  It can be done by a synthesis tool or a point tool.  Whichever tool is used, remember that there’s no guarantee a chain will work without first fixing any issues uncovered by the DRCs.  Make sure the tool supports whichever type of scan design is required (e.g. mux scan or LSSD).  

Chain Stitching –The most important requirement for stitching is that the resulting chain shift safely.  The merging of different clock domains and clock edges onto a chain must be carefully handled by either proper ordering or the insertion of additional lock-up cells to avoid hold time problems.  Other important considerations might include chain balancing, ordering from a scan “DEF” file, stitching pre-existing chains in sub-blocks and supporting hierarchical techniques which require some form of wrapper chains.
To summarize, comprehensive DRCs are critical in identifying testability issues and is critical to guaranteeing success.  An intuitive debugging environment is the biggest factor in making users productive and resolving issues quickly.  The scan cell insertion and chain stitching must be flexible enough to accommodate different design flows and DFT methodologies.

Next Issue's Product/Service Focus
In our next issue of Product/Service Focus we will cover All/VXI. You can add or upgrade a listing before the next issue comes out.

If you would like to include an exclusive article on how to best select All/VXI, please contact

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New Definitions
New terms added to the Test Definition section:
Built-In Repair Analysis
Burst Mode
Burst-Ready Block Module
Capture by Domain
Double Data Rate Synchrounous Dynamic Random Accses Memory
Embedded Logic Test
LAN eXtensions for Instrumentation
Serializer / Deserializer
Utopia Bus
We now have 2238 test terms in our Test Definition section.

Share your definitions with the test community.