Reach the thousands of test professionals we mail to. Sponsor The BestTest Newsletter and we will place your logo here.

Visit the A.T.E. Solutions, Inc. Booth #1258 at 

AutoTestCon 2007

in Baltimore, MD on Sept 18-20, 2007 and win an iPod!

Make an appointment to discuss our new service for test vendors

Come to a Half-Day Tutorial at AutoTestCon

Design for Built-In Self Test

by Louis Y. Ungar at AutoTestCon in Baltimore, MD on Sept 17, 2007

Come to a Three-Day Course

Random Vibration and Shock Testing, HALT, ESS, HASS

in Albuquerque, New Mexico on October 3-5, 2007

Come to a Three-Day Course

Design for Testability and for Built-In Self Test

by Louis Y. Ungar in St. Louis, MO on October 22-24, 2007

Come to a One-Day Course

Cost Effective Tests Using ATE, DFT and BIST 

by Louis Y. Ungar in Los Angeles, CA on November 20, 2007

By Arden Bjerkeli,

There’s an old saying about being caught between a rock and a hard place. That’s how test engineers often feel when they’re trying to diagnose faults on circuit boards with chips in ball grid array (BGA) packages. They feel that way because many times that’s where those hard-to-find and impossible-to-see BGA faults are: caught between the device and the printed circuit board.

Boundary scan (JTAG) test systems excel at finding, isolating and diagnosing faults where test pads are few and far between, and where access to device pins is absent. Most designs that feature BGAs do so for a reason. Significant functionality has to go on the circuit board, so it is densely populated with space-saving chips such as BGAs. Because board real estate is at a premium, there are few, if any, test pads on these designs. And, using BGAs further exacerbates the test diagnosis problem, since the bonding balls beneath the chip are not visible to the human eye or optical inspection equipment. As an access-free, electrical test technology, JTAG can be a very effective tool at diagnosing BGA-related faults.

Diagnosing What?

Electronic test has three distinct purposes: detecting failures, diagnosing faults to the level of a replaceable unit, and diagnosing faults to the level of their root causes in order to prevent future failures. To varying degrees the various test technologies such as functional test and several structural test techniques like JTAG/boundary scan, in-circuit test (ICT), X-ray inspection and others can supplement each other to achieve all three facets of electronic test and diagnostics. But, in the final analysis, boundary scan has certain capabilities that no other test technology has and these make it particularly effectively at diagnosing BGA faults.

Functional test set-ups, which typically implement several types of test technologies, are designed to ensure that the product can perform the designer’s intended functions. As such, functional test may detect classes of failures that structural test may not detect. For this reason, functional test is usually an important component in a design’s test strategy. Unfortunately, while functional test can effectively detect failures, it is not so effective at taking the next step and diagnosing those the faults to the replaceable unit or to their root causes.

For example, a test technician may run a functional test routine and determine that a failure occurs on a circuit board. The type of function that failed may suggest that the problem stems from a BGA, but the technician doesn’t know where the fault is. For instance, a short or an open could be under the device package, or the device itself could be bad, or a short/open could be present somewhere else on the circuit board entirely.

The test technician is then faced with a dilemma. He can remove the BGA from the circuit board to determine whether there is a fault underneath the die, but, in doing so, he will damage the bonding balls and will either have to throw away the chip or incur added an expense re-attaching the bonding balls to the die. In addition, removing the BGA device will destroy any visible evidence of where the fault might have been. In the end, the technician could decide to replace the BGA device on the circuit board, run the same functional test routine and observe whether the failure has been fixed. If the failure persists, the technician might begin to wonder whether the fault is somewhere else on the circuit board or whether he replicated the same fault underneath the BGA a second time. Furthermore, since it is often undetermined whether the nature of the fault was structural or functional, the quality of the removed BGA is unknown. The ambiguity and frustration mounts geometrically.

Underneath the Rocks

Structural test technologies like boundary scan or ICT are able to detect shorts and opens, and, more importantly, diagnose where they are. Unfortunately, ICT requires that the circuit board have test points designed into it for ICT’s bed-of-nails probes. Typically, designs that deploy compact BGA devices do so because board real estate is scarce. As a result, test points are typically hard to come by and the use of ICT equipment for structural test and diagnostics may be quite limited.

In contrast, JTAG does not need any test points on the board. Test vectors can be scanned to the BGA from connected devices to determine whether shorts or opens are present. Boundary-scan tests for opens can often determine which termination of the net is open, even if the termination is under the BGA. In some cases, a net may have terminations under multiple BGAs, so knowing the exact location of the open can prevent the removal of the wrong BGA.

Following the Roots

Process engineers frequently want to take this one step further and find the root cause of shorts and opens so that flaws in the manufacturing process can be corrected to eliminate recurring faults. When this is the case, X-ray inspection can be used in tandem with JTAG to diagnose root causes. Once faults are detected by boundary scan, X-ray inspection may be used to look under the BGA to determine the root cause, such as insufficient or excessive paste or an uneven reflow temperature. And if the certainty that a fault was structural in nature can be increased, fewer BGAs will be falsely indicted as malfunctioning.

Ultimately, boundary-scan test provides a very effective set of diagnostic tools that test engineers, test technicians and process engineers can put to good use locating and isolating faults relating to devices in BGA packages on printed circuit boards. When boundary scan is complemented with other techniques, such as X-ray inspection and functional test, the costs of producing printed circuit boards with BGAs can be tamed.

By Stephan Pateras, Ph.D.,

The traditional ATPG-based silicon bring-up flow represents a significant component of the product development cycle and can often take weeks if not months to complete. These delays are getting even worse with the adoption of at-speed and ATPG compression methodologies. This lengthy bring-up process not only represents significant engineering costs but more importantly a delay in getting working samples to the end customer and therefore a direct impact to the product launch timeline. Any reductions in the bring-up time will therefore have a direct effect on the success and eventually the profitability of the device. 

LogicVision’s BIST based bring-up flow is significantly simpler than the traditional ATPG-based flow and removes much of the complexity for the designer. Rather than having to create test patterns to run specific tests, the design engineer simply specifies easy to understand high level test options in a configuration file or through an interactive GUI. Automation software then controls the tester to communicate with the various on-chip BIST resources to perform the desired tests and then extract and interpret the results. Since all of the BIST resources have been verified during the design phase, there is no test related debug to perform on the tester. In fact, minimal test equipment is needed as the only requirements are communication to the standard five-pin JTAG test interface and the delivery of power and clocking to the device. Power and clocking are often provided within a performance board environment. In this case no test equipment is required and communication to the JTAG port can be achieved with a simple PC or laptop connected to a USB-to-JTAG interface cable. This not only reduces the cost associated with tying up an expensive tester, but also allows bring-up activity to occur anytime, and thus further accelerates the overall bring-up process.

LogicVision’s Silicon Insight™ provides a fully interactive graphical environment for diagnosing and characterizing circuitry tested using LogicVision’s BIST capabilities. Silicon Insight works on most ATEs as well as on any Linux PC or laptop as described above (see figure 1). Silicon Insight’s graphical environment provides a visual representation of the BIST resources within the device and the order in which they are to be executed. BIST controllers are represented as individual icons within the main GUI panel. All BIST controller settings and options as well as the overall execution order can be modified interactively using the GUI.

For example in the GUI display shown in figure 2, three memory BIST controllers (BP4, BP5 and BP6) are displayed along with their most recent execution results. The display shows that BIST controller BP5 has detected failures and that these failures are associated with only one of the four tested memories (shown as bidirectional arrows). More details on the failing memory can be easily generated. Failing memory, memory port, and memory I/O information are generated instantaneously and displayed both graphically as well as sent to a datalog file for future processing. Bit level failure information can also be quickly generated (figure 3). For each failure the tool displays: the failing memory port, the failing row and column addresses and bit position, the algorithm used to test the memory and the phase of this algorithm in which the failure was detected. This information is displayed in text format for each failure as well as provided in a table summary format for easier analysis. Similar diagnostic capabilities are also provided for logic. Both static and at-speed failures can be diagnosed down to the pattern, flip-flop (figure 4) and even gate level (figure 5).

Silicon Insight also supports circuit performance characterization. A built-in Shmoo tool allows measuring a circuit’s performance across any voltage and/or frequency range. Performance can also be measured under various circuit activity levels. For example, a memory’s maximum frequency can be logged when no other circuit activity exists within the chip, when only certain other memories are active or when all memories are being exercised. If logic BIST is also being used, then the logic activity level can also be controlled. All activity levels are easily set within the graphical environment and require no specific knowledge of the BIST or the design. This detailed and interactive characterization capability is very powerful in determining specific design areas (e.g. memories, logic blocks or paths) that are the slowest and thus limiting the overall speed of the design.

More efficient silicon bring-up strategies are becoming a must as product windows continue to decrease. The combination of BIST with automated diagnostic software provides a drastic improvement in both bring-up and characterization timelines. With these capabilities, first silicon is typically up and running at-speed within a matter of hours of having received samples from the foundry.

• If your friend forwarded this newsletter to you, please register as a member and receive The BestTest Newsletter -- absolutely free!
• If you wish to update your news preferences or cancel the subscription, please unsubscribe.
• If you have any questions, please email experts@BestTest.com

Get the widest selection of test related books and software at the BestTest Online Store.

Introducing
The Testability Director Version 3.2
 

Reach the thousands of test professionals we mail to.
Place Ad here.

2007-2008