A.T.E. Solutions Info
About Us
Contact Us
Site Map
Short Cuts
Online Store
Books on Test
Build a Test Library
Testability Director Software
Test Flow Simulator Software
Schedule of Courses
On-Site Courses
ConsulTraining
Test Requirements Analysis
TRD and TPS Development
Testability Consulting
BIST Consulting
ATE Market Consulting
Consultant Reports
BITES single-chip Built-In Tester
BestTest Directory
Test Calendar
Test Definitions
Articles on Test
Test Vendor Directory
Test Products and Services Directory
Advertising

Design for Testability and Built-In Self Test for Boards and Systems

Admin/IMGLOAD/1-testability.gif
What you will learn:
You will be exposed to structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, and by the recently released IEEE-1687 standards. The course will cover memory BIST, logic BIST and analog BIST and how they can be used for board and system test. It will also cover built-in test (BIT) software, and its goal to provide diagnostic information. You will obtain convincing reasons for utilizing DFT and BIST techniques in your organization's board and system design.
Abstract:
The course will highlight board and system-level manufacturing test and supportability issues. In order to achieve the unambiguous isolation of the faulty circuits, testability has to be assessed at the design stage often before the circuit details are known. We will examine how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course will evaluate the value of DFT and BIST at all levels of assembly from an economic perspective. You will leave the course with a thorough understanding of techniques, and guidelines you can put to use right away to manage automatic test and ATE at your company. The DFT and BIST methods will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs.

Who should attend:
This course is not only of interest to designers and test engineers, but it will also be of great value to reliability, logistics, quality and manufacturing engineers. Managers concerned with testability and BIST techniques as part of DFX, as well as those with general interest of IEEE and military standards in DFT should find this course a great value.


Detail:

Design for Testability (DFT) and Built-In Self Test (BIST) for Boards and Systems Course Outline

DAY 1

Introduction

  • Test Concepts and Automatic Testing
  • Definitions
  • DFT Why, What, Who, When?
  • Built-In Test (BIT), Embedded Test and Built-In Self Test (BIST)
  • Ad hoc Design for Testability

Structured DFT and BIST

  • Fault Models and Simulation
  • Automatic Test Pattern Generation (ATPG) when is it possible?
  • Scan Concepts
  • Boundary Scan (JTAG/IEEE-1149.1)
  • Scan Standards for ICs (IEEE-1500, 1149.7)
  • Logic BIST
  • Memory BIST
  • Diagnoses with Scan and BIST
  • IDDQ Testing

Board Level DFT and BIST

  • Electronic Manufacturing Test Strategies
  • JTAG and IEEE-1149.1, .4, .6
  • PCOLA/SOQ for various test strategies
  • Probing and Fixturing Guidelines
  • Flying Probe Testability Guidelines
  • Vectorless Test and the IEEE-1149.8.1
  • Automatic Optical and X-Ray Inspectability
  • Electrical Design Guidelines
  • Analog DFT and BIST
  • Towards a Contactless Board Level Test

DAY 2

System Level DFT and BIST

  • System Level Functional Test
  • Diagnosis and Integrated Diagnostics
  • Failure Mode Effects (Criticality) Analysis
  • Guidelines of MIL-STD-2165
  • Built-In Test Software
  • Dependency Modeling
  • SJTAG and the IEEE-1149.x for System Repair
  • False Alarms and Incorrect Isolation

Hierarchical DFT and BIST

  • Hierarchical Test and Repair
  • DFT and BIST Repair Strategies
  • What will IEEE-1687 bring?

DFT and BIST Economics

  • Repair or not lack of test is bad economics, or is it?
  • What are we really saving expressed in financial terms
  • Justifying and selling DFT and BIST
  • Managing DFT and BIST

Summary and Advanced Concepts to Ponder

  • Remote Test and Diagnoses
  • Prognostics and Health Management
  • How DFT and BIST affect security and counterfeiting
  • Built-In Self Repair

Instructor: Louis Y. Ungar
Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. El Segundo, CA. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management. As a test engineer, Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs for dozens of ATEs. As a design engineer he designed payload systems for the Space Shuttle, eventually leading a team of designers. With both engineering and management experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly respected test and testability consulting and educational firm. Mr. Ungar serves as Testability Committee Chair for the Surface Mount Technology Association (SMTA), as Consultant to the American Society of Test Engineers (ASTE), the founding President of the Testability Management Action Group (TMAG) and various test and testability groups of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on the IEEE-1149.1-2013 and the IEEE-1687. He is also involved with the Testability section of a Design for Excellence (DFX) Guideline by the IPC to be published in 2015. He can be reached at LouisUngar at ieee.org.


Availability:
FormatDateLengthLocationPrice
Onsite Define 2 days 
RFQ
Private Define 2 days 
RFQ
Public Define2-15-162 daysBarcelona, Spain
RESERVE NOW
RFQ