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WebCourse - Design for Testability 101 - Who, What, When, Why, How Much

What you will learn:
You will learn why Design for Testabilty (DFT) is an invaluable method to reduce test development costs. As long as DFT is performed early in the design stage, the return on investment (ROI) is substantial. You will learn how to translate techinical issues involving testability to economic issues understood by non-technical management.
This short introduction to the topic of DFT will cover the considerations that go into making test decisions early enough to influence the design. At the early stages testability is often trivial and even without cost, but if they are ignored test is compromised and its costs prohibitively increased. Designers, product developers, managers and test engineers need to know what DFT entails. This webinar provides that information regardless of your technical background.

Who should attend:
Everyone in the product development team - designers, test engineers, manufacturing engineers, product managers and even marketing personnel will find this one hour webinar an important eye opener.


Design for Testability DFT 101 - Who, What, When, Why and How Much?

The following topics will be explored in this webinar:

  • Types of Tests and their Requirements
  • Some Basic Definitions
  • Test Program Development
  • What is Design for Testability (DFT) and Why We Need It?
    • Motivations for Testable Design
    • Benefits of Concurrent Engineering
    • Cost Reductions through DFT
    • Overcoming Untestables and Hard-to-Tests
  • DFT Attributes
  • DFT Metrics
  • DFT for ICs
    • What is Scan?
  • DFT for Circuit Boards
    • What is Boundary Scan?
  • DFT for Systems
    • Failure Mode Effects Analysis (FMEA) and DFT
    • Diagnosability
  • Economics of DFT
  • Beyond DFT
    • Built-In Self Test (BIST)
    • Prognostics and Health Management
    • Built-In Self Repair

This is the first of a series of Webinars on the subject.  Others, presented in consecutive lectures include:
   DFT 201 - Techniques for ICs, Boards and Systems
   DFT 301 - JTAG/Boundary Scan/IEEE-1149.1
   DFT 401 - System Level Testability and Diagnosabiity
   DFT 501 - Advanced Techniques: IEEE-1149.4, .6, .7, P1687

Instructor: Louis Y. Ungar
Louis Y. Ungar is president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and Testability courses at the University of California at Los Angeles (UCLA) and throughout industry. Mr. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the Surface Mount Technology Association and has served on committees for various IEEE standards, including those of IEEE Std. 1149.x. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management.

Webinar7-12-101.5 hour webinarWebCourse Start - 10 AM Pacific, 1 PM EST, 18:00 GMT$199.50
Onsite Define 1.5 hour webinarOn Demand$599.50