What you will learn:
You will learn specific Design for Testabilty (DFT) techniques for making your circuit more testable, whether the circuit is an Integrated Circuit, Circuit Board, or a System. This course provides the "How" that was not covered in DFT 101. You will learn easy to apply techniques to circuits that will reap substantial benefits when it comes time to test the circuit.
The techniques demonstrated in this webinar are rather simple to apply in the early stages of the design and produce great returns on investment when it comes time to test the circuit. The subject matter requires only basic understanding of electronics. While more sophisticated and structural approaches exist and will be discussed in detail in other webinars, this webinar provides a good overview of the techniques that exist and may be sufficient for an overview of the subject of Design for Testability.
Who should attend:
Everyone in the product development team - designers, test engineers, manufacturing engineers, product managers and even marketing personnel will find this to be a good introduction to the subject matter, without necessarily getting involved in the details of testability electronics.
Design for Testability DFT 201 - Techniques for ICs, Boards and Systems
The following topics will be explored in this webinar:
- Testability Differences between ICs, Boards and Systems
- Differences between Ad Hoc Testability and Structured Testability
- Structured Testability for ICs
- The Concept of Scan
- Level Sensitive Scan Design (LSSD)
- Other Scan Techniques
- Board Level Testability
- Inspectability for Automatic Optical Inspection (AOI)
- Inspectability for X-Ray (AXI)
- Guided Probing
- Bed-of-Nails Accessibility
- Vectorless Testing
- Boundary Scan (JTAG or IEEE-1149.1)
- Non Intrusive Board Test
- System Level Testability
- Fault Detection and Fault Isolation
- Integrated Diagnostics
- Testability Metrics
This is the second in a series of Webinars on the subject. Others, presented in consecutive lectures include:
DFT 101 - Who, What, When, Why and How Much?
DFT 301 - JTAG/Boundary Scan/IEEE-1149.1
DFT 401 - System Level Testability and Diagnosabiity
DFT 501 - Advanced Techniques: IEEE-1149.4, .6, .7, P1687
Instructor: Louis Y. Ungar
Louis Y. Ungar is president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and Testability courses at the University of California at Los Angeles (UCLA) and throughout industry. Mr. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the Surface Mount Technology Association and has served on committees for various IEEE standards, including those of IEEE Std. 1149.x. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management.