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WebCourse - Design for Testability 301 - JTAG/Boundary Scan/IEEE 1149.1

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What you will learn:
You will learn the details of Boundary Scan, often called, JTAG and officially called the IEEE-1149.1 standard. While you may have come across this concept, you may still be a bit unsure if you have a clear understanding. In this webinar we look under the hood and you will learn the intricate details of how this technology works.
Abstract:
Treatment of JTAG, Boundary Scan and IEEE-1149.1 leaves users and researchers a bit confused - it is not even clear sometime which of these names you should use for the technology. This short webinar will unravel the mysteries. We will explore the machine language level operations, come up to the higher level command structure and get to the point where you will feel more comfortable with using commercial test development software available from various vendors.

Who should attend:
Anyone planning to utilize Boundary Scan, whether in design, in test, in field service, in embedded test will gain an understanding of this important phenomenon.


Detail:

Design for Testability DFT 301 - JTAG/Boundary Scan/IEEE 1149.1

The following topics will be explored in this webinar:

  • Historical Perspective
    • Is there a difference between JTAG, Boundary Scan and IEEE-1149.1?
  • What can it do and what  is its purpose?
  • The Boundary Scan Structure
  • The Boundary Scan Cell
  • The Test Access Port (TAP)
  • Non-Invasive Operational Modes 
    • Bypass 
    • ID Code Insturction
    • Sample/Preload
  • Pin-Permission Operational Modes
    • EXTEST
    • INTEST
    • RUNBIST
    • High Z
    • CLAMP
  • Boundary Scan Description Language (BSDL)
  • Boundary Scan Tests - Automatically Generated
    • TAP Integrity Test
    • Wrong Component Test
    • Boundary Scan In-Circuit Test
    • Virtual Interconnect Test
    • Virtual Component/Cluster Test
    • Boundary Functional Test
  • Scan I/O and Boundary Scan Testers
  • What is missing from the IEEE-1149.1 Standard

This is the third of a series of Webinars on the subject.  Others, presented in consecutive lectures include:
   DFT 101 - Who, What, When, Why, How Much?
  
DFT 201 - Techniques for ICs, Boards and Systems

   DFT 401 - System Level Testability and Diagnosabiity
   DFT 501 - Advanced Techniques: IEEE-1149.4, .6, .7, P1687


Instructor: Louis Y. Ungar
Louis Y. Ungar is president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and Testability courses at the University of California at Los Angeles (UCLA) and throughout industry. Mr. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the Surface Mount Technology Association and has served on committees for various IEEE standards, including those of IEEE Std. 1149.x. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management.


Availability:
Format Date Length Location Price
Webinar 7-14-10 1.5 hour webinar WebCourse Start - 10 AM Pacific, 1 PM EST, 18:00 GMT $199.50
Onsite Define   1.5 hour webinar On Demand $599.50