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WebCourse - Design for Testability 401 - System Level Testability and Diagnosability

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What you will learn:
For system level, testability isn't only failure detection. You need to concern yourself with repair and before that can happen, you need to accurately and unambigously determine the root cause of the system failure. That root cause should involve a single replaceable subsystem or board in nearly all cases. You will learn how to approach this in a logical fashion.
Abstract:
System level testability and diagnosability involves more than just the ability to identify output signal correctness. Diagnosability is even more difficult and often perfectly detectable systems suffer from an inherent inability to diagnose the root cause to a single replaceable unit. By performing proper analysis early in the design stage, however, one can ensure that the resulting system not only can be tested to detect failures, but that the cause of these failures will reside in a single replaceable unit. This webinar will teach you how to perform Fault Tree analysis and how to calculate reliability weighted diagnostic resolution.

Who should attend:
System developers, test engineers, reliability engineers and those involved in support functions will find this webinar enlightening.


Detail:

Design for Testability DFT 401 - System Level Testability and Diagnosability

The following topics will be explored in this webinar:

  • Diagnostics - Definitions and Examples
  • Diagnostic Models
  • Traditional Field Service
  • Fault Tree Example
    • Unweighted
    • Reliability Weighted
    • Other Weighting
  • Failure Mode Effects Analysis
    • Causes
    • Effects
    • Severity and Criticality
    • Frequency Rating
  • Integrated Diagnostics
  • Dependency Modeling
  • Calculating Penalty Costs
  • Prognostics and Health Management

This is the fourth of a series of Webinars on the subject.  Others, presented in consecutive lectures include:
   DFT 101 - Who, What, When, Why, How Much?
  
DFT 201 - Techniques for ICs, Boards and Systems
   DFT 301 - JTAG/Boundary Scan/IEEE-1149.1

   DFT 501 - Advanced Techniques: IEEE-1149.4, .6, .7, P1687

 


Instructor: Louis Y. Ungar
Louis Y. Ungar is president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and Testability courses at the University of California at Los Angeles (UCLA) and throughout industry. Mr. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the Surface Mount Technology Association and has served on committees for various IEEE standards, including those of IEEE Std. 1149.x. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management.


Availability:
Format Date Length Location Price
Webinar 7-15-10 1.5 hour webinar WebCourse Start - 10 AM Pacific, 1 PM EST, 18:00 GMT $199.50
Onsite Define   1.5 hour webinar On Demand $599.50