A.T.E. (Advanced Test Engineering) Solutions, Inc.
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Online Catalog of Educational Courses and Resources
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Welcome to the Online Catalog of Courses and Educational Resources. There are many ways we have for you to find what you want from this catalog:
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23 Records Found
What You Will Learn
A Unified Approach for Timing Verification and Delay Fault Testing
A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Accelerated Reliability Engineering: HALT and HASS
Accelerated reliability engineering is becoming a popular industry alternative to on-going product quality testing. Highly Accelerated Life Tests (HALT) and Highly Accelerated Stress Screens (HASS) are intensive methods, which use stresses higher than the field environments to expose and then improve design and process weaknesses. HALT and HASS offer faster, cheaper and more accurate results than traditional reliability testing techniques. This book provides comprehensive coverage of the methods and philosophy behind this successful approach. Production managers will appreciate the time-saving and cost-effective testing techniques described. Design engineers involved in quality assurance and students of reliability engineering will benefit from this unique resource detailing the technical aspects of accelerated reliability engineering. Features Include: · Coverage of the physics of failure and useful testing equipment enabling those new to the area to grasp the concepts behind HALT and HASS · Overview of the HALT technique demonstrating how to find design and process defects quickly using accelerated stress methodology during the design phase of the project · Examination of detection screens and modulated excitation used to detect flaws exposed in HALT · Description of how to set up a HASS profile and how to minimize costs whilst retaining efficiency · Applications of HALT and HASS and analysis of common mistakes highlighting the pitfalls to avoid when implementing the methods
Accelerated Stress Testing Handbook: Guide for Achieving Quality Products
Electrical Engineering Accelerated Stress Testing Handbook Guide for Achieving Quality Products As we move closer to a genuinely global economy, the pressure to develop highly reliable products on ever-tighter schedules will increase. Part of a designer's "toolbox" for achieving product reliability in a compressed time frame should be a set of best practices for utilizing accelerated stress testing (AST). The Accelerated Stress Testing Handbook delineates a core set of AST practices as part of an overall methodology for enhancing hardware product reliability. The techniques presented will teach readers to identify design deficiencies and problems with component quality or manufacturing processes early in the product's life, and then to take corrective action as quickly as possible. A wide array of case studies gleaned from leading practitioners of AST supplement the theory and methodology, which will provide the reader with a more concrete idea of how AST truly enhances quality in a reduced time frame. Important topics covered include: * Theoretical basis for AST * General AST best practices * AST design and manufacturing processes * AST equipment and techniques * AST process safety qualification In this handbook, AST cases studies demonstrate thermal, vibration, electrical, and liquid stress application; failure mode analysis; and corrective action techniques. Individuals who would be interested in this book include: reliability engineers and researchers, mechanical and electrical engineers, those involved with all facets of electronics and telecommunications product design and manufacturing, and people responsible for implementing quality and process improvement programs.
Analog Test and Fault Isolation
The problems that you will encounter when you try to test analog circuits with an ATE. The course will show how accuracies and resolutions can affect your test results. You will also learn to deal with analog simulation and fault simulation issues. The IEEE-1149.4 Mixed Signal Testability as well as the IEEE-1149.6 mechanisms will also be explored.
Design for Excellence
This course will teach you how to design a product that is manufacturable, testable, reliable, useable, electromagnetically compatible, maintainable and supportable. In short, an electronic product that not only functions but is made to be of excellent value to you and to your customer.
Design for Testability and Built-In Self Test for Boards and Systems
You will be exposed to structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, and by the recently released IEEE-1687 standards. The course will cover memory BIST, logic BIST and analog BIST and how they can be used for board and system test. It will also cover built-in test (BIT) software, and its goal to provide diagnostic information. You will obtain convincing reasons for utilizing DFT and BIST techniques in your organization's board and system design.
Design for Testability and for Built-in Self Test
In this comprehensive course you will learn all aspects of Design for Testability (DFT), from what it is, why you might need it, why someone would object to it, and what it can and cannot accomplish. You will learn how today's technology has become elusive to certain failure modes and how important it is to expose them through more testable designs. This 3-day class will encompass DFT techniques for ICs, ASICs, SoCs, FPGAs, boards, systems, and even prognostic health management. First you will learn some simple techniques to enhance observability and controllability. You will learn how you can access hundreds of internal points with as few as four additional edge connector pins. You will learn specific guidelines for both digital and analog circuit testability. You will learn structured testability techniques, such as internal and boundary-scan. You will come away with a deep understanding of the IEEE 1149.1 (JTAG) standard's operation, use and even its limitations. You will also learn later standards, such as IEEE-1149.4, .6, .7 as well as IEEE-1500, 1532, 1581 and 1687. You will also learn some new techniques in testability, including IDDQ testing and I/O Mapping. In the second part of the course, you will learn what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. With these building blocks you will be able to evaluate a number of BIST architectures for Logic BIST and Memory BIST. You will learn BIT Software techniques and consider the effect false alarms have on BIT. You will finally be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions.
Electronic Failure Analysis Handbook
Still digging for the latest developments and techniques in electronic failure analysis? The leading-edge methods for slashing product failure rates are all right here in this complete, comprehensive source. You'll find top-to-bottom coverage of this rapidly developing field, encompassing breakthrough techniques and technologies for both components and systems reliability testing, performance evaluation, and liability avoidance. Absolutely essential to anyone concerned with electronic product development and testing, the Handbook gives you ready-to-use, insider information on state-of-the-art EFA techniques; the how's and why's of electronic failures; failure prediction; warranty cost control; liability-costs and other issues.
Environmental and Reliabilty Testing
This course covers the environmental and reliability tests performed during design and in manufacturing. You will learn about reliability prediction techniques and factors. You will learn what you can expect from reliability growth testing environmental stress screening (ESS). You will know how environmental stress screening (ESS) is used to flush out flaws introduced during processing, fabrication and assembly. When highly accelerated for longer duration, this is called Reliability Test. You will learn how Reliability Test can flush out design flaws resulting from incompatible interfaces, from erroneous functional performance in different environments and from weak components. By the completion of this course you will be able to formulate environmental and reliability test strategies for your own products.
ESD Design and Analysis Handbook
Electrostatic Discharge (ESD) is a pervasive issue in the semiconductor industry affecting both manufacturers and users of semiconductors. The problem worsens with each new generation of parts and components. As technology scales to higher levels of integration, circuits become more sensitive to ESD and the design of protection becomes more difficult. ESD Design and Analysis Handbook presents an overview of ESD as it effects electronic circuits and provides a concise introduction for students, engineers, circuit designers and failure analysts. This handbook is written in simple terms and is filled with practical advice and examples to illustrate the concepts presented. While this treatment is not exhaustive, it presents many of the most important areas of the ESD problem and suggests methods for improving them. The key topics covered include the physics of the event, failure analysis, protection, characterization, and simulation techniques. The book is intended as both an introductory text on ESD and a useful reference tool to draw on as the reader gains experience. The authors have tried to balance the level of detail in the ESD Design and Analysis Handbook against the wealth of literature published on ESD every year. To that end, each chapter has a topical list of references to facilitate further in-depth study.
ESD in Silicon Integrated Circuits
Introduces the basic mechanisms involved in electrostatic discharge (ESD) events, the physical processes that take place in a semiconductor, and circuit design for ESD protection. Written for engineers who design ICs and transistors, the book addresses such topics as the physics of devices under high current and high voltage conditions, layout techniques for input/output pins, and failure mode analysis. The second edition adds a chapter on circuit simulation.
Failure Analysis of Integrated Circuits: Tools and Techniques
Failure Analysis of Integrated Circuits: Tools and Techniques provides a basic understanding of how the most commonly used tools and techniques in silicon-based semiconductors are applied to understanding the root cause of electrical failures in integrated circuits. These include applications specific to performing failure analysis such as decapsulation, deprocessing, and fail site isolation, as well as physical and chemical analysis tools and techniques. The coverage is qualitative, and it provides a general understanding for making intelligent tool choices. Also included is coverage of the shortcomings, limitations, and strengths of each technique.
Failure Mode and Effects Analysis (FMEA)
You will learn how to prepare and utilize FMEA to improve reliability, safety, testability, and maintainability. This course will describe FMEA methodology and its multiple uses for a more reliable, testable and maintainable product.
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications
Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.
How to Design for Testability (DFT) for Today's Boards and Systems
Detailed review of the various guidelines covered in the SMTA/TMAG Testability Guidelines. Part 1 of the Webtorial will introduce attendees to the issues surrounding testing of electronic circuit boards and systems. It introduces testing concept and the mix of testers normally used. This includes the JTAG/IEEE-1149.1 boundary scan as well as built-in self test (BIST). With a combination of these technologies, the idea of non-intrusive board (and system) test is explored. The Webtorial takes the view that DFT is the best way to improve test performance and cost effectiveness. Towards that end Part 2 provides specific DFT guidelines. It concludes with exploring new standards and developments in DFT that will improve testing of boards and systems in the future.
Microelectronic Reliability, Vol 1
Let twelve specialists show you how to test, analyze, and achieve better microelectronic reliability of silicon and GaAs devices. Microelectronic Reliability, Volume I: Reliability, Test, and Diagnostics offers you detailed, original works on the topics most vital to both device and equipment reliability and manufacturing yield. Broad enough to serve as an effective textbook and in-depth enough for practicing engineers, this text also makes an ideal reference for managers who need a quick overview of current reliability, test, and failure analysis issues. Supported by 600 references, 147 figures, and 39 tables, this encyclopedic guide shows you how to identify the thermal, chemical, and mechanical processes that influence the incidence and severity of failure mechanisms. This coverage outlines techniques for assessing the susceptibility to failure of various devices. Detailing the theory and operation of current failure analysis tools, the text also gives you instrument price ranges and example analyses. Combined with the sweeping overview and comprehensive bibliography found in Microelectronic Reliability Volume II, this text gives you the only source you need to meet today's ever-improving standards for quality and reliability of advanced microelectronic technology. Contents: Preface. Introduction. Statistical Aspects for Reliability. Failure Mechanisms in Microelectronic Devices. Testability for Functional Verification and Diagnostics. Automatic Testing. Manufacturing Process Control. GaAs Reliability and Test. Appendix A: Advanced Failure Analysis Instrumentation. List of Acronyms. Glossary. Index.
On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective
This comprehensive and insightful book discusses ESD protection circuit design problems from an IC designer's perspective. On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective provides both fundamental and advanced materials needed by a circuit designer for designing ESD protection circuits, including: · Testing models and standards adopted by U.S. Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc. · ESD failure analysis, protection devices, and protection of sub-circuits · Whole-chip ESD protection and ESD-to-circuit interactions · Advanced low-parasitic compact ESD protection structures for RF and mixed-signal IC's · Mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions, and more! Many real world ESD protection circuit design examples are provided. The book can be used as a reference book for working IC designers and as a textbook for students in the IC design field.
Optimizing Electronics Vibration HALT, HASS, ALT and ESS
A three-day interactive workshop aimed at shortening the time required for electronics design, vibration testing and (when weaknesses are found) corrective action. This course applies to vibration of electronics at system, box or circuit card level. Methods can also be used in the design and testing of electronic components to meet vibration standards or desired capabilities. Discussion of simple methods and animations assist participants understand the complex responses of their electronics to laboratory and to field vibration. "Vibration test efficiency" is a new term, used here to illustrate recent improvements over the past slow "learning curve" for vibration knowledge. Since vibration life of most electronics is dependent on response at circuit card level, methods concentrate on the fatigue damage from PCB modal response. The purpose of this course is to simplify the complex field of vibration of electronics and make results understandable. 1% Efficiency? Tests can determine fragility limits of test samples. But few tests supply any further information (beyond pass/fail). Why? Because test measurements can't fully describe failures. Most tests miss most of the valuable information that is (with this course) readily available. Early Attempts In the 70's and 80's, relatively simple mathematical methods were developed to predict PCB vibration life capabilities. Why? Because few companies could afford that era's high-speed computer systems and the technical expertise needed to analyze vibration. Those early methods, still used by many, provide guidelines that sometimes work, but they never provide product understanding. And all too often, such guidelines outright fail, at great expense - the expense of design and production of an unreliable product. But since then, the cost of high-speed computer power has dropped at a rate of about 50% per year. The compounded cost savings of the mid 80's high-speed computer is over 99.99%. One of the best-kept secrets of certain large companies is their ability to produce reliable electronic products at low cost. How? They are able to fully understand vibration of their electronics through detailed analysis. Such companies rarely share their reliability secrets with competitors. But now, with this course, every company can afford high speed analysis support of its testing. Test Efficiency? Let's define test efficiency as dollar value of information gained divided by dollars of test cost. If you run a test program without analysis, your numerator is near zero. Adding modern technology analysis can immeasurably increase your "information gained" numerator. Every test performed without detailed posttest analysis throws information away and wastes money. Rather than throw it away, capture that information and use it to save many design and production problems. Detailed Analysis? The "design life" of any system is defined by its weakest part based on the part's local exposure. Since vibration damage of circuit cards is dominated by cyclic stresses (caused by modal vibration), analysis should concentrate on accurately quantifying the stresses experienced by every component. Design life is limited by accumulated fatigue damage. Taking advantage of the speed of today's PCs, companies without prior experience can use this course to understand and avoid vibration-induced failures. For DATES AND LOCATIONS see
Software Test, Reliability and Quality Assurance
You will get practical answers to the following questions: When should you start testing and when can you stop testing? How do you predict software bug rates? Which defects are acceptable and why? What software metrics should be collected to measure testing progress? How do you plan for testing, debugging, and fixing software? What can you look for in code to verify that software reliability has been designed into the software? This course prepares you to create better software and to evaluate software produced by others.
Standards in Test
You will be introduced to most of the Military and Commercial Standards that affect the way test is performed and interpreted by both military and commercial concerns.
VLSI Simulation and Test Generation
The stuck-at models used in simple logic is becoming obsolete when we wish to test Very Large Scale Integrated circuits. You will learn new approaches to test that can be used to test highly complex circuits.
WebCourse - Design for Testability 101 - Who, What, When, Why, How Much
You will learn why Design for Testabilty (DFT) is an invaluable method to reduce test development costs. As long as DFT is performed early in the design stage, the return on investment (ROI) is substantial. You will learn how to translate techinical issues involving testability to economic issues understood by non-technical management.
WebCourse - Design for Testability 401 - System Level Testability and Diagnosability
For system level, testability isn't only failure detection. You need to concern yourself with repair and before that can happen, you need to accurately and unambigously determine the root cause of the system failure. That root cause should involve a single replaceable subsystem or board in nearly all cases. You will learn how to approach this in a logical fashion.
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