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Online Catalog of Educational Courses and Resources
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27 Records Found
What You Will Learn
A Designer's Guide to Built-in Self-Test
Part of the
DFT/BIST Library Collection.
A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test (BIST). This idea was first proposed around 1980 and has grown to become one of the most important testing techniques at the current time, as well as for the future. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented since 1980, along with their advantages and limitations. The BIST approaches include the Built-In Logic Block Observer, pseudo-exhaustive BIST techniques, Circular BIST, scan-based BIST, BIST for regular structures, BIST for FPGAs and CPLDs, mixed-signal BIST, and the integration of BIST with concurrent fault detection techniques for on-line testing. Particular attention is paid to system-level use of BIST in order to maximize the benefits of BIST through reduced testing time and cost as well as high diagnostic resolution. The author spent 15 years as a designer at Bell Labs where he designed over 20 production VLSI devices and 3 production circuit boards. Sixteen of the VLSI devices contained BIST of various types for regular structures and general sequential logic, including the first BIST for Random Access Memories (RAMs), the first completely self-testing integrated circuit, and the first BIST for mixed-signal systems at Bell Labs. He has spent the past 10 years in academia where his research and development continues to focus on BIST, including the first BIST for FPGAs and CPLDs along with continued work in the area of BIST for general sequential logic and mixed-signal systems. He holds 10 US patents (with 5 more pending) for various types of BIST approaches. Therefore, the author brings a unique blend of knowledge and experience to this practical guide for designers, test engineers, product engineers, system diagnosticians, and managers.
A Unified Approach for Timing Verification and Delay Fault Testing
A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Boundary-Scan Interconnect Diagnosis
Boundary-Scan Interconnect Diagnosis explains how to synthesize digital diagnostic sequences for wire interconnects using boundary-scan, and how to assess the quality of those sequences. Its importance has to do with designing complex electronic systems using pre-designed intellectual property (IP) cores, which is becoming increasingly popular nowadays. Since tests for pre-designed cores can be supplied with the cores themselves, the only additional tests that need to be developed to test and diagnose the entire system are those for wire interconnects between the cores. Besides the trivial solutions that are often used to solve this problem, there are many more methods that enable significant optimizations of test vector length and/or diagnostic resolution. The book surveys all existing methods of this kind and proposes new ones. In the new approach circuit and interconnect faults are carefully modeled, and graph techniques are applied to solve the problem. The original feature of the new method is the fact that it can be adjusted to provide shorter test sequences and/or greater diagnostic resolution. The effectiveness of existing and proposed methods is then evaluated using real electronic assemblies and published statistical data for an actual manufacturing process from HP.
Cost Effective Tests Using ATE, DFT and BIST
The two main reasons to test are 1) to eliminate failures escaping to your customers and 2) to reduce the life cycle cost of a product by eliminating penalty costs associated with delivering potentially faulty units. Many people have traded one of these requirements for the other, but with the advent of more sophisticated automatic test equipment (ATE), more attention paid to design for testability (DFT) and utilizing built-in self test (BIST), it is possible to do both. This tutorial provides a thorough understanding of each of these tools and strategies for more comprehensive and cost-effective testing. The course will combine the technical aspects of testing today’s complex circuits with the economics demanded by lower costs, faster times to market and a higher rate of obsolescence for both electronic products and test equipment.
Design for AT-Speed Test, Diagnosis and Measurement
Design for AT-Speed Test, Diagnosis and Measurement offers practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design makes this book a `must read' before any DFT is attempted.
Design for Excellence
This course will teach you how to design a product that is manufacturable, testable, reliable, useable, electromagnetically compatible, maintainable and supportable. In short, an electronic product that not only functions but is made to be of excellent value to you and to your customer.
Design for Testability and Built-In Self Test for Boards and Systems
You will be exposed to structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, and by the recently released IEEE-1687 standards. The course will cover memory BIST, logic BIST and analog BIST and how they can be used for board and system test. It will also cover built-in test (BIT) software, and its goal to provide diagnostic information. You will obtain convincing reasons for utilizing DFT and BIST techniques in your organization's board and system design.
Digital Systems Testing and Testable Design
This widely-used textbook provides comprehensive, state-of-the-art coverage of digital systems testing and testable design. Considered a definitive text in this area, the book includes in-depth discussions of the following topics: Test generation Fault modeling for classic and new technologies Simulation Fault simulation Design for testability Built-in self-test (BIST) Diagnosis All topics are covered extensively, from fundamental concepts to advanced techniques. Successfully used world-wide at leading universities, the book is appropriate for graduate-level and senior-level undergraduate courses. Numerous examples and problems help make the learning process easier for the reader. Test engineers, ASIC and system designers, and CAD developers will find it an invaluable tool to keep current with recent changes in the field.
Electronic Testing and Fault Diagnosis, 3rd Edition
Electronic Testing and Fault Diagnosis is a highly practical guide to the theory and methods of testing electronic circuits and systems. The third edition has been fully revised to provide up-to-date coverage of standard test procedures and reliability and maintainability analysis for most analog and digital electronic circuits and components. An introduction to automatic test equipment (ATE) is included, as well as data on passive and active components.
EMI Troubleshooting Techniques
Stop EMI, EMD and RFI cold! Now you can get the newest, most effective weapons to fight costly and potentially devastating electromagnetic interference (EMI), electromagnetic discharge (EMD), and radio frequency interference (RFI) in the field or on the bench. EMI Troubleshooting Techniques, by Michel Marduian, arms you with an arsenal of fail-safe, time- and labor-saving diagnostic routines to help you pinpoint and lock out even the most persistent interference problems. Its 4-step approach lets you 1) identify specific (and even hidden) trouble symptoms, 2) find the matching solutions, 3) implement them and 4) understand their strengths and limitations. From power line filters and conduction type fixes to transient suppressors and radiation control, this time-and money-saving guide streamlines robust designs, speeds on-site troubleshooting for industrial-strength applications, and simplifies EMC lab testing for optimal result. Plus, you get a variety of recommended filters, isolation transformers, shields, varistors, grounding and impedance devices, tapes, foils, and more. The EMI/RFI problems stop here. When you have got an electrical noise or interference problem this reference is all you need to diagnose and solve it in a hurry. EMI Troubleshooting Techniques presents an orderly, methodical approach to locating the cause of and correcting EMI/RFI breakdowns. It gives you hands-on, optimal solutions whether your task is design, lab testing, or on-site troubleshooting, no matter what type of electronic equipment you are handling. Written by veteran EMC designer/troubleshooter Michel Mardiguian, this efficiency-boosting guide is just what you are looking for in a practical solutions kit--and more. It offers: a solution matrix that helps you pinpoint the right fix quickly; a walk-through chart that simplifies the troubleshooting process; EMI-reduction components categorized by indications, applications, and limitations; practical alternatives to lab testing methods; consideration of real-life issues such as costs, time constraints, and accessibility; solutions for most electronic environments. Whether the EMI in a cars automatic-locking mechanism, a medical diagnostic tool, or a computer motherboard, and whether you are developing, prototyping, testing, diagnosing, or applying fixes, there is only one EMI reduction kit virtually guaranteed to help you avoid dead ends and wasted time: EMI Troubleshooting Techniques.
Fundamentals of Semiconductor Manufacturing and Process Control
Fundamentals of Semiconductor Manufacturing and Process Control covers all issues involved in manufacturing microelectronic devices and circuits, including fabrication sequences, process control, experimental design, process modeling, yield modeling, and CIM/CAM systems. Readers are introduced to both the theory and practice of all basic manufacturing concepts. Following an overview of manufacturing and technology, the text explores process monitoring methods, including those that focus on product wafers and those that focus on the equipment used to produce wafers. Next, the text sets forth some fundamentals of statistics and yield modeling, which set the foundation for a detailed discussion of how statistical process control is used to analyze quality and improve yields. The discussion of statistical experimental design offers readers a powerful approach for systematically varying controllable process conditions and determining their impact on output parameters that measure quality. The authors introduce process modeling concepts, including several advanced process control topics such as run-by-run, supervisory control, and process and equipment diagnosis.
How to Design for Testability (DFT) for Today's Boards and Systems
Detailed review of the various guidelines covered in the SMTA/TMAG Testability Guidelines. Part 1 of the Webtorial will introduce attendees to the issues surrounding testing of electronic circuit boards and systems. It introduces testing concept and the mix of testers normally used. This includes the JTAG/IEEE-1149.1 boundary scan as well as built-in self test (BIST). With a combination of these technologies, the idea of non-intrusive board (and system) test is explored. The Webtorial takes the view that DFT is the best way to improve test performance and cost effectiveness. Towards that end Part 2 provides specific DFT guidelines. It concludes with exploring new standards and developments in DFT that will improve testing of boards and systems in the future.
IDDQ Testing of VLSI Circuits
Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Integrated Diagnostics and Artificial Intelligence
How integrated diagnostics and artificial intelligence (AI) can be used to improve product support. You will learn the basic principals of artificial intelligence and how they apply to test and diagnosis. You will also learn diagnostic concepts, including dependency modeling and optimizations.
Microelectronic Reliability, Vol 1
Let twelve specialists show you how to test, analyze, and achieve better microelectronic reliability of silicon and GaAs devices. Microelectronic Reliability, Volume I: Reliability, Test, and Diagnostics offers you detailed, original works on the topics most vital to both device and equipment reliability and manufacturing yield. Broad enough to serve as an effective textbook and in-depth enough for practicing engineers, this text also makes an ideal reference for managers who need a quick overview of current reliability, test, and failure analysis issues. Supported by 600 references, 147 figures, and 39 tables, this encyclopedic guide shows you how to identify the thermal, chemical, and mechanical processes that influence the incidence and severity of failure mechanisms. This coverage outlines techniques for assessing the susceptibility to failure of various devices. Detailing the theory and operation of current failure analysis tools, the text also gives you instrument price ranges and example analyses. Combined with the sweeping overview and comprehensive bibliography found in Microelectronic Reliability Volume II, this text gives you the only source you need to meet today's ever-improving standards for quality and reliability of advanced microelectronic technology. Contents: Preface. Introduction. Statistical Aspects for Reliability. Failure Mechanisms in Microelectronic Devices. Testability for Functional Verification and Diagnostics. Automatic Testing. Manufacturing Process Control. GaAs Reliability and Test. Appendix A: Advanced Failure Analysis Instrumentation. List of Acronyms. Glossary. Index.
On Line-Testing for VLSI
Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.
PC Troubleshooting Pocket Book Third Edition
The Newnes PC Troubleshooting Pocket Book provides a concise and compact reference that describes, in a clear and straightforward manner, the principles and practice of faultfinding and upgrading PCs and peripherals. The book is aimed at anyone who is involved with the installation, configuration, maintenance, upgrading, repair or support of PC systems. It also provides non-technical users with sufficient background information, charts and checklists to enable the diagnosis of faults and help to carry out simple modifications and repairs. The new edition of PC Troubleshooting will continue to include a number of short cuts that are instrumental in avoiding hours of potential frustration and costly effort. In order to reflect rapid changes in computer technology (both hardware and software) the third edition of the Newnes PC Troubleshooting Pocket Book has been completely revised and rewritten. New and expanded sections on: modern machines (Pentium II, III, IV, AMD); modern buses (FSB, AGP, Cyrix, Chip sets); different RAM chip types, performance and guide to RAM connectors; Win2000, ME, XP and NT4/5; latest SCSI standards, Ultra DMA, “live” re-portioning of the disc, FAT 16, FAT36, NTFS, performance and compatibility differences; ‘famous’ viruses and personal firewalls.
Research Perspectives and Case Studies in Systems Test and Diagnosis
System level testing is becoming increasingly important. It is driven by the incessant march of complexity ... which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is 'any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail'. System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress. The works included in this volume are an outgrowth of the 2nd International Workshop on System Test and Diagnosis held in Alexandria, Virginia in April 1998. The first such workshop was held in Freiburg, Germany, six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject... In this volume, a select group of workshop participants was invited to provide a chapter that expanded their workshop presentations and incorporated their workshop interactions... While we have attempted to present the work as one volume and requested some revision to the work, the content of the individual chapters was not edited significantly. Consequently, you will see different approaches to solving the same problems and occasional disagreement between authors as to definitions or the importance of factors.... The works collected in this volume represent the state-of-the-art in system test and diagnosis, and the authors are at the leading edge of that science...
Software Design for Testability (SDFT)
The latest theory and practice of Software Design for Testability (SDFT) will be explained, primarily through comparisons and analogies to the well-established discipline of hardware DFT.
Standards in Test
You will be introduced to most of the Military and Commercial Standards that affect the way test is performed and interpreted by both military and commercial concerns.
Thermal Testing of Integrated Circuits
Temperature has been always considered as an appreciable magnitude to detect failures in electric systems. Abnormal status of this variable, both too high and too low, is sign of abnormal behavior in electronic systems. In Thermal Testing of Integrated Circuits the authors present the feasibility to consider temperature as an observable for testing purposes. The coupling of circuits thtough heat is inherent to the solid-state nature and the inspection of temperature does not interact with Under Test Circuits or Systems, something that does not happen when voltage or current observable are used. In the book the basis of heat propagation, heat conducting mechanisms and temperature sensitivity of semiconductors are focused with a full coverage of the state of the art. We usually have the idea that all the heating processes are slow, which is true in the macroscopic world, but is not in the case of integrated circuits where the reduced size and amount of material and the really high conductivity of substrates make the thermal testing a promising technique. CMOS and BICMOS temperature sensors for built-in thermal testing are presented in the book. The application of temperature as testing magnitude for both on-line and off-line, analog or digital, on-chip or off-chip are considered. The temperature sensing has an inherent directional capability that can be used as an element for localizing failures, so the technique has interesting diagnosis capabilities as well.
VLSI Simulation and Test Generation
The stuck-at models used in simple logic is becoming obsolete when we wish to test Very Large Scale Integrated circuits. You will learn new approaches to test that can be used to test highly complex circuits.
WebCourse - Design for Testability 101 - Who, What, When, Why, How Much
You will learn why Design for Testabilty (DFT) is an invaluable method to reduce test development costs. As long as DFT is performed early in the design stage, the return on investment (ROI) is substantial. You will learn how to translate techinical issues involving testability to economic issues understood by non-technical management.
WebCourse - Design for Testability 201 - Techniques for ICs, Boards and Systems
You will learn specific Design for Testabilty (DFT) techniques for making your circuit more testable, whether the circuit is an Integrated Circuit, Circuit Board, or a System. This course provides the "How" that was not covered in DFT 101. You will learn easy to apply techniques to circuits that will reap substantial benefits when it comes time to test the circuit.
WebCourse - Design for Testability 301 - JTAG/Boundary Scan/IEEE 1149.1
You will learn the details of Boundary Scan, often called, JTAG and officially called the IEEE-1149.1 standard. While you may have come across this concept, you may still be a bit unsure if you have a clear understanding. In this webinar we look under the hood and you will learn the intricate details of how this technology works.
WebCourse - Design for Testability 401 - System Level Testability and Diagnosability
For system level, testability isn't only failure detection. You need to concern yourself with repair and before that can happen, you need to accurately and unambigously determine the root cause of the system failure. That root cause should involve a single replaceable subsystem or board in nearly all cases. You will learn how to approach this in a logical fashion.
WebCourse - Design for Testability 501 - Advanced DFT Techniques
Boundary Scan pioneered a new approach to testability for board level. It is, however, important to integrate this with other forms of assembly. For today's complex circuits it may not be sufficient to test the boundary of the IC. Rather we will need to test inside the IC even when the IC is already mounted on a circuit board and when that board is already part of a module or system. This webinar will teach you about newer tools and the integration of those tools with traditional testability approaches.
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