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What You Will Learn
A Designer's Guide to Built-in Self-Test
Part of the
DFT/BIST Library Collection.
A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test (BIST). This idea was first proposed around 1980 and has grown to become one of the most important testing techniques at the current time, as well as for the future. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented since 1980, along with their advantages and limitations. The BIST approaches include the Built-In Logic Block Observer, pseudo-exhaustive BIST techniques, Circular BIST, scan-based BIST, BIST for regular structures, BIST for FPGAs and CPLDs, mixed-signal BIST, and the integration of BIST with concurrent fault detection techniques for on-line testing. Particular attention is paid to system-level use of BIST in order to maximize the benefits of BIST through reduced testing time and cost as well as high diagnostic resolution. The author spent 15 years as a designer at Bell Labs where he designed over 20 production VLSI devices and 3 production circuit boards. Sixteen of the VLSI devices contained BIST of various types for regular structures and general sequential logic, including the first BIST for Random Access Memories (RAMs), the first completely self-testing integrated circuit, and the first BIST for mixed-signal systems at Bell Labs. He has spent the past 10 years in academia where his research and development continues to focus on BIST, including the first BIST for FPGAs and CPLDs along with continued work in the area of BIST for general sequential logic and mixed-signal systems. He holds 10 US patents (with 5 more pending) for various types of BIST approaches. Therefore, the author brings a unique blend of knowledge and experience to this practical guide for designers, test engineers, product engineers, system diagnosticians, and managers.
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Analog Signal Generation for Built-In-Self-Test (BIST) of Mixed-Signal Integrated Circuits is a concise introduction to a powerful new signal generation technique. It begins with a brief introduction to the testing problem and a review of conventional signal generation techniques. The book then describes an oversampling-based oscillator capable of generating high-precision analog tones using a combination of digital logic and D/A conversion. These concepts are then extended to multi-tone testing schemes without introducing a severe hardware penalty. The concepts are extended further to encompass piece-wise linear waveforms such as square, triangular and sawtooth waves. Experimental results are presented to verify the ideas in each chapter and finally, conclusions are drawn. For those readers unfamiliar with delta-sigma modulation techniques, a brief introduction to this subject is also provided in an appendix. The book is ideal for test engineers, researchers and circuits designers with an interest in IC testing methods.
Built-In Test: Bridge From Design Through Support
This book was written for use by various disciplines. It clearly describes the use if BIT, BITE, Self-Test and BIST, from the perspective of Designers, Test Engineers, Support and Management. It distinguishes between component, board and system application of BIT and illustrates implementation for each. The reader is introduced to scan techniques, Linear Feedback Shift Registers, signature analyzers, Pseudo-Random Signal Generators and other BIT design tools. Analog BIT is also covered. Finally, techniques are given to evaluate BIT design in terms of fault detection, fault isolation, false alarm rates, as well as its effect on maintainability, MTTR, Operational Readiness and Availability.
Cost Effective Tests Using ATE, DFT and BIST
The two main reasons to test are 1) to eliminate failures escaping to your customers and 2) to reduce the life cycle cost of a product by eliminating penalty costs associated with delivering potentially faulty units. Many people have traded one of these requirements for the other, but with the advent of more sophisticated automatic test equipment (ATE), more attention paid to design for testability (DFT) and utilizing built-in self test (BIST), it is possible to do both. This tutorial provides a thorough understanding of each of these tools and strategies for more comprehensive and cost-effective testing. The course will combine the technical aspects of testing today’s complex circuits with the economics demanded by lower costs, faster times to market and a higher rate of obsolescence for both electronic products and test equipment.
Design for Excellence
This course will teach you how to design a product that is manufacturable, testable, reliable, useable, electromagnetically compatible, maintainable and supportable. In short, an electronic product that not only functions but is made to be of excellent value to you and to your customer.
Design for Testability and Built-In Self Test for Boards and Systems
You will be exposed to structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, and by the recently released IEEE-1687 standards. The course will cover memory BIST, logic BIST and analog BIST and how they can be used for board and system test. It will also cover built-in test (BIT) software, and its goal to provide diagnostic information. You will obtain convincing reasons for utilizing DFT and BIST techniques in your organization's board and system design.
Design for Testability and for Built-in Self Test
In this comprehensive course you will learn all aspects of Design for Testability (DFT), from what it is, why you might need it, why someone would object to it, and what it can and cannot accomplish. You will learn how today's technology has become elusive to certain failure modes and how important it is to expose them through more testable designs. This 3-day class will encompass DFT techniques for ICs, ASICs, SoCs, FPGAs, boards, systems, and even prognostic health management. First you will learn some simple techniques to enhance observability and controllability. You will learn how you can access hundreds of internal points with as few as four additional edge connector pins. You will learn specific guidelines for both digital and analog circuit testability. You will learn structured testability techniques, such as internal and boundary-scan. You will come away with a deep understanding of the IEEE 1149.1 (JTAG) standard's operation, use and even its limitations. You will also learn later standards, such as IEEE-1149.4, .6, .7 as well as IEEE-1500, 1532, 1581 and 1687. You will also learn some new techniques in testability, including IDDQ testing and I/O Mapping. In the second part of the course, you will learn what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. With these building blocks you will be able to evaluate a number of BIST architectures for Logic BIST and Memory BIST. You will learn BIT Software techniques and consider the effect false alarms have on BIT. You will finally be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions.
Design-For-Test For Digital IC's and Embedded Core Systems
The first practical DFT guide from an industry insider. Skip the high-brow theories and mathematical formulas—get down to the business of digital design and testing as it's done in the real world. Learn practical testing strategies that address today's business needs for quality, reliability, and cost control, working within the tight deadlines of typical high-pressure production environments. Design-for-Test for Digital IC's and Embedded Core Systems helps you optimize the engineering trade-offs between such resources as silicon area, operating frequency, and power consumption, while balancing the corporate concerns of cost-of-test, time-to-market, and time-to-volume. You'll also boost your efficiency with the special focus on automatic test pattern generation (ATPG). The book includes a roadmap that allows you to fine-tune your learning if you want to skip directly to a specific subject. Key topics include: Core-based design, focusing on embedded cores and embedded memories System-on-a-chip and ultra-large scale integrated design issues AC scan, at-speed scan, and embedded DFT Built-in self-test, including memory BIST, logic BIST, and scan BIST Virtual test sockets and testing in isolation Design for reuse, including reuse vectors and cores Test issues being addressed by VSIA and the IEEE P1500 Standard Design-for-Test for Digital IC's and Embedded Core Systems is filled with full-page graphics taken directly from the author's teaching materials. Every section is illustrated with flow-charts, engineering diagrams, and conceptual summaries to make learning and reference fast and easy. This book is a must for the engineers and managers involved in design and testing. The enclosed CD-ROM contains full-color versions of all the book's illustrations in Acrobat PDF format. These images may be viewed interactively on screen or printed out to create overheads for teaching. Acrobat Reader software for Windows and UNIX computers is included.
Digital Circuit Testing and Testability
This is an easy to use introduction to the practices and techniques in the field of digital circuit testing. The author writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.
Digital Circuit Testing: A Guide to DFT and Other Technologies
Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to these and other testing techniques. For each technique introduced, the author provides real-world examples so the reader can achieve a working knowledge of how to choose and apply these increasingly important testing methods.
Digital Hardware Testing
Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path. Contents:Faults in Digital Circuits. Bridging Faults in Random Logic. Open Circuit Faults in Random Logic. Fault Simulation and Test Generation. Testing of Structured Designs (PLAs). Memory Testing. Testing of Sequential Circuits. Microprocessor Testing. Design for Testability. Current Testing. Special Test Methods.
Digital Systems Testing and Testable Design
This widely-used textbook provides comprehensive, state-of-the-art coverage of digital systems testing and testable design. Considered a definitive text in this area, the book includes in-depth discussions of the following topics: Test generation Fault modeling for classic and new technologies Simulation Fault simulation Design for testability Built-in self-test (BIST) Diagnosis All topics are covered extensively, from fundamental concepts to advanced techniques. Successfully used world-wide at leading universities, the book is appropriate for graduate-level and senior-level undergraduate courses. Numerous examples and problems help make the learning process easier for the reader. Test engineers, ASIC and system designers, and CAD developers will find it an invaluable tool to keep current with recent changes in the field.
Eben Hewitt's ColdFusion Training Course: A Digital Seminar on CD-ROM
Start creating ColdFusion enterprise applications right now -- visually! · A fully-integrated eBook/QuickTime video package: more than 5 hours of expert personal training from Eben Hewitt, one of the world's most experienced ColdFusion developers! · Includes easy-to-adapt source code for key enterprise applications -- XML, WML, SQL/database integration, Web mail, and much more. · Bonus! Eben Hewitt's best-selling Core ColdFusion 5 in fully searchable electronic format. Web developers and designers live in a visual world -- and now there's a visual way to master ColdFusion 5's most powerful capabilities: Eben Hewitt's ColdFusion Training Course! Your personal instructor is Eben Hewitt, creator of ColdFusion sites visited by more than two million people each month. Watch as he builds enterprise-class Web applications right before your eyes -- and listen, as he explains every step. You'll learn a broad range of essential ColdFusion techniques, encompassing the ColdFusion language and application server, administration, content serialization with XML, SQL, wireless deployment, and more. The course offers practical insight into advanced ColdFusion 5 features, including user-defined functions, query-of-queries, data-driven Macromedia Generator graphs, custom tags, and more. Your CD-ROM contains all the source files you'll need to follow along. You also get a 250-page printed workbook -- plus a comprehensive eBook, Core ColdFusion 5, accessible with one click from anywhere in the course. As you practice, test yourself with exercises -- and extend your knowledge with the CD-ROM's extensive resource center, full of additional ColdFusion readings and Web links. Eben Hewitt is a Macromedia Certified ColdFusion Developer, a certified Microsoft SQL Server Administrator, and Director of Production for Creative Services at Cybertrails.com. A frequent ColdFusion Developer's Journal columnist, he is a member of the ColdFusion Edge faculty, and author of Core ColdFusion 5. Every month, nearly two million people visit the ColdFusion sites he has created.
Finding a useful guide to the principles of electronic troubleshooting was a problem in itself for professional technicians and hobbyists. Not anymore. This updated tool gives them all the fundamentals they need to do successful servicing and repair work, blending traditional theory with the very latest insight into modern electronics technology. Time-saving tables, charts, and illustrations pinpoint equipment problems in a snap. Numerous reference guides, rules of thumb, and tricks of the trade all combine to assist them in troubleshooting the full spectrum of devices and products more easily than ever before.
Embedded Processor-Based Self-Test
Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit’s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design. Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment.
Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories
From PDAs to supercomputers, cell phones to video games, every modern electronic system contains memory -- most often, RAM. As engineers seek to increase the power and capacity of these systems, they are introducing advanced new nanofabrication CMOS technologies. In these environments, today's processing techniques are no longer sufficient to produce high-yield wafers. To improve RAM reliability without compromising performance, cost, or space requirements, engineers are turning to advanced fault-tolerant techniques. This is the first book to survey the state-of-the-art in memory fault tolerance. KEY TOPICS:The authors survey the latest research and new field-proven techniques for reliable and fault-tolerant RAM circuit design and evaluation, placing these advances in the context of the field's progress over the past two decades. They examine both manufacturing fault-tolerance (e.g. self-repair at the time of manufacturing) and online and field-related fault-tolerance (e.g. error-correction). The book presents in-depth discussions of each key requirement for RAM design, and each key technique -- including rationale, advantages, disadvantages, design flow, implementation, and results. MARKET: For every professional concerned with VLSI/memory circuit design, testing, and reliability, including semiconductor and VLSI design and test engineers and other design team members working in industry; engineers working on SOC (system-on-a-chip) and embedded products; and electrical engineering researchers and advanced students throughout academia.
High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test
Design and test are considered jointly in this book since knowledge of one without the other is insufficient for the task of having high quality memories. Knowledge of memory design is required to understand test. An understanding of test is required to have effective built-in self-test implementations. A poor job can be done on any of these pieces resulting in a memory that passes test but which is not actually good. The relentless press of Moore's law drives more and more bits onto a single chip. The large number of bits means that methods that were "gotten away with" in the past will no longer be sufficient. Because the number of bits is so large, fine nuances of fails that were rarely seen previously now will happen regularly on most chips. These subtle fails must be caught or else quality will suffer severely. Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.
High-Level Test Synthesis of Digital VLSI Circuits
This is the first book to propose HTS as a complete, effective design approach to derive an inherently testable architecture at low or even no overhead. The book presents a background to HTS, discusses various HTS techniques for both scan and built-in self-test methodologies, covers register transfer level test synthesis, and introduces high-level synthesis algorithms. It provides examples of several effective HTS schemes for highly testable digital circuits and a survey of representative HTS systems.
How to Design for Testability (DFT) for Today's Boards and Systems
Detailed review of the various guidelines covered in the SMTA/TMAG Testability Guidelines. Part 1 of the Webtorial will introduce attendees to the issues surrounding testing of electronic circuit boards and systems. It introduces testing concept and the mix of testers normally used. This includes the JTAG/IEEE-1149.1 boundary scan as well as built-in self test (BIST). With a combination of these technologies, the idea of non-intrusive board (and system) test is explored. The Webtorial takes the view that DFT is the best way to improve test performance and cost effectiveness. Towards that end Part 2 provides specific DFT guidelines. It concludes with exploring new standards and developments in DFT that will improve testing of boards and systems in the future.
How to Use BestTest.com to Market Your Courses
You will learn how easily you can place your course on our web site and thereby advertise it to the thousands of engineering professionals that frequent BestTest.com in persuit of engineering knowledge.
IDDQ Testing of VLSI Circuits
Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Introduction to Advanced System-on-Chip Test Design and Optimization
Test design is applied to make a system testable. In a modular core-based environment where blocks of reusable logic, the so called cores, are integrated to a system, test design for each core include: test method selection, test data (stimuli and responses) generation (ATPG), definition of test data storage and partitioning [off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST (Built-In Self-Test)], wrapper selection and design (IEEE std 1500), TAM (test access mechanism) design, and test scheduling minimizing a cost function whilst considering limitations and constraint. A system test design perspective that takes all the issues above into account is required in order to develop a globally optimized solution. SOC test design and its optimization is the topic of this book. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.
LabWindows/CVI Programming for Beginners (With CD-ROM)
The first "teach yourself" guide for LabWindows/CVI! LabWindows/CVI is the #1 system for building Windows-based virtual instrumentation with ANSI C—and this hands-on, project-oriented guide is the fastest way to get results with LabWindows/CVI! You'll master all you need to know to build programs that control instruments and data acquisition hardware—while still taking advantage of an easy-to-use user interface editor for building Windows applications. Shahid F. Khalid presents never-before-published LabWindows/CVI tips and tricks—plus coverage of every key LabWindows/CVI skill you'll need, including: * Systematically creating effective GUIs and automatically generating C code * Learning the tips and tricks of the Source Code Editor and Debugger * Learning the library functions through the use of Function Panels * Creating applications using File I/O, List Boxes, Rings, Text Box controls, and many more * Creating standalone executables, distribution disks, Dynamic Link Libraries (DLLs), and using the application from a supported external compiler * Complete tutorial on communication with instruments using GPIB and RS-232 interfaces Each chapter is organized for maximum clarity and convenience, and you'll find handy appendices explaining the features of LabWindows/CVI environment, formatting and scanning functions, and tutorial on two demo programs. If you're a LabWindows/CVI novice, you'll learn fast—and once you do, LabWindows/CVI Programming for Beginnerswill serve you well as a reference for years to come. CD-ROM INCLUDED The accompanying CD-ROM includes a complete trial version of LabWindows/CVI 5.5, plus finished versions of every project covered in the book. The CD-ROM also comes with complete trial versions of a System Test application and a mathematical application that analyzes functions parametrically
On Line-Testing for VLSI
Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.
Power-Constrained Testing of VLSI Circuits
Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.
Practical Radio Frequency Test and Measurement A Technician's Handbook
The book will teach readers the basics of performing the tests and measurements used in radio-frequency systems installation, proof of performance, maintenance, and troubleshooting. Practical Radio Frequency Test and Measurement teaches readers the basics of performing the tests and measurements used in radio-frequency systems installation, proof of performance, maintenance, and troubleshooting. Anyone interested in gaining more practical proficiency with RF, whether engineer, technician, amateur radio buff, or hobbyist, needs a copy of this book. Joseph J. Carr, himself an accomplished practitioner in this field, examines the instruments used in the various types of measurement before moving on to specific measurement methods. Carr includes information on basic theories of RF measurement, as well as test equipment, test set-ups, test and measurement procedures, and interpretation of results.
Research Perspectives and Case Studies in Systems Test and Diagnosis
System level testing is becoming increasingly important. It is driven by the incessant march of complexity ... which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is 'any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail'. System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress. The works included in this volume are an outgrowth of the 2nd International Workshop on System Test and Diagnosis held in Alexandria, Virginia in April 1998. The first such workshop was held in Freiburg, Germany, six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject... In this volume, a select group of workshop participants was invited to provide a chapter that expanded their workshop presentations and incorporated their workshop interactions... While we have attempted to present the work as one volume and requested some revision to the work, the content of the individual chapters was not edited significantly. Consequently, you will see different approaches to solving the same problems and occasional disagreement between authors as to definitions or the importance of factors.... The works collected in this volume represent the state-of-the-art in system test and diagnosis, and the authors are at the leading edge of that science...
Test and Design-For-Testability in Mixed-Signal Integrated Circuits
Test and Design-for-Testability in Mixed-Signal Integrated Circuits deals with test and design for test of analog and mixed-signal integrated circuits. Especially in System-on-Chip (SoC), where different technologies are intertwined (analog, digital, sensors, RF); test is becoming a true bottleneck of present and future IC projects. Linking design and test in these heterogeneous systems will have a tremendous impact in terms of test time, cost and proficiency. Although it is recognized as a key issue for developing complex ICs, there is still a lack of structured references presenting the major topics in this area. The aim of this book is to present basic concepts and new ideas in a manner understandable for both professionals and students. Since this is an active research field, a comprehensive state-of-the-art overview is very valuable, introducing the main problems as well as the ways of solution that seem promising, emphasizing their basis, strengths and weaknesses. In essence, several topics are presented in detail. First of all, techniques for the efficient use of DSP-based test and CAD test tools. Standardization is another topic considered in the book, with focus on the IEEE 1149.4. Also addressed in depth is the connecting design and test by means of using high-level (behavioural) description techniques, specific examples are given. Another issue is related to test techniques for well-defined classes of integrated blocks, like data converters and phase-locked-loops. Besides these specification-driven testing techniques, fault-driven approaches are described as they offer potential solutions which are more similar to digital test methods. Finally, in Design-for-Testability and Built-In-Self-Test, two other concepts that were taken from digital design, are introduced in an analog context and illustrated for the case of integrated filters. In summary, the purpose of this book is to provide a glimpse on recent research results in the area of testing mixed-signal integrated circuits, specifically in the topics mentioned above. Much of the work reported herein has been performed within cooperative European Research Projects, in which the authors of the different chapters have actively collaborated. It is a representative snapshot of the current state-of-the-art in this emergent field.
The Design for Testability and Built-In Self Test (DFT/BIST) Library Collection
We selected 21 of the best books on the subjec for your company library with the intent of providing all the information you need to understand Design for Testability and Built-In Self-Test for analog, digital, mixed signal, board-leve, system-level,system-on-a-chip and even for a formal approach. The combined list price of individual books is considerably higher. We update the selections based on availability and how they apply to current needs. See a list in
The Test Library Collection
The Economics of Test and Testability
Why test is a solution to an economic problem How non-technical management views return on investment (ROI) and how to translate technical benefits to these terms Existing formulas for the cost and benefits of IC, board, and system tests How behavioral economics applies to test and what we can learn from it.
Using WAVES and VHDL for Effective Design and Testing
The proliferation and growth of Electronic Design Automation (EDA) has spawned many diverse and interesting technologies. One of the most prominent of these technologies is the VHSIC Hardware Description Language, or VHDL. VHDL permits designers of digital modules, components, systems, and even networks to describe their designs both structurally and behaviorally. VHDL also allows simulation of the designs in order to investigate their performance prior to actually implementing them in hardware. Having gained the ability to simulate designs once encoded in VHDL, designers were naturally confronted with the issue of testing these designs. VHDL did not explicitly address the requirement to insert particular digital waveforms, often termed test vectors or patterns, or to subsequently assess the correctness of the response from some digital entity. In a distributed design environment, or even in an isolated one where the design was subject to review or scrutiny by another organization, de-facto methods of testing and evaluating results proved faulty. The reason was a lack of standardization. When organization A designed a circuit and tested it with their self-developed test tools it had a certain behavior. When it was delivered to organization B and B tested it using their test tools, the behavior was different. Was the fault in the circuit, in A's tools, or in B's tools? The only way to resolve this was for both organizations to agree on a test apparatus, validate its correctness and use it consistently. While VHDL was an IEEE standard language, and consistency among myriad designers was fairly well guaranteed, no such standard existed for test waveform generation and assessment. Hence, the value of standardization in the design language was being negated by the lack of such a standard for testing. The Waveform and Vector Exchange Specification, or WAVES, was conceived and designed to solve this testing problem - and it has. Being both a subset of VHDL itself, as well as an IEEE standard, it guarantees both conformity among multiple applications and easy integration with VHDL units under test (UUTs). Using WAVES and VHDL for Effective Design and Testing will serve many purposes. For the WAVES beginner, its tutorial will make the application of WAVES in typical, standard usage straightforward and convenient. For the more advanced user, the advanced topics will provide insight into the nuances of these useful capabilities. For all users, the tools, templates and examples given in the chapters, as well as on the companion disk, will provide a practical starting foundation for using WAVES and VHDL.
VLSI Simulation and Test Generation
The stuck-at models used in simple logic is becoming obsolete when we wish to test Very Large Scale Integrated circuits. You will learn new approaches to test that can be used to test highly complex circuits.
VLSI Test Principles and Architectures: Design for Testability
This book combines in a unique way insight into industry practices commonly found in commercial DFT tools but not discussed in textbooks, and a sound treatment of the future fundamentals. The comprehensive review of future test technology trends, including self-repair, soft error protection, MEMS testing, and RF testing, leads students and researchers to advanced DFT research.
WebCourse - ATE 101 - Overview of Test, ATE & Testability
A participant who has little or no background in test can leave this course with a thorough understanding of the issues. While the course provides few solutions, it is imperative that anyone making decisions concerning test and testability should first attend this course.
WebCourse - Design for Testability 101 - Who, What, When, Why, How Much
You will learn why Design for Testabilty (DFT) is an invaluable method to reduce test development costs. As long as DFT is performed early in the design stage, the return on investment (ROI) is substantial. You will learn how to translate techinical issues involving testability to economic issues understood by non-technical management.
WebCourse - Design for Testability 401 - System Level Testability and Diagnosability
For system level, testability isn't only failure detection. You need to concern yourself with repair and before that can happen, you need to accurately and unambigously determine the root cause of the system failure. That root cause should involve a single replaceable subsystem or board in nearly all cases. You will learn how to approach this in a logical fashion.
WebCourse - Design for Testability 501 - Advanced DFT Techniques
Boundary Scan pioneered a new approach to testability for board level. It is, however, important to integrate this with other forms of assembly. For today's complex circuits it may not be sufficient to test the boundary of the IC. Rather we will need to test inside the IC even when the IC is already mounted on a circuit board and when that board is already part of a module or system. This webinar will teach you about newer tools and the integration of those tools with traditional testability approaches.
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