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Online Catalog of Educational Courses and Resources


Page 1 of 3 of Users' Guide
Welcome to the Online Catalog of Courses and Educational Resources. There are many ways we have for you to find what you want from this catalog:
  1. Using the "Search for Topic or Format-Text" box you can filter the selections by
      a. Keywords, such as "in-circuit," "environment," etc.
      b. Course formats, such as "public," "private," etc.
  2. Read the "What You Will Learn" section next to each course.
  3. For each course of interest, you can click the hyperlinked "Details" to see the detailed course outline.
  4. Check the "Select" button next to titles that are of interest to you.
  5. Press the "More on Selected Titles" button to see what formats and dates are available for these selected courses.
Search for Topic or Format-Text:
46 Records Found
Select A Title What You Will Learn Details
  An Introduction to Mixed-Signal IC Test and Measurement Integrated circuits incorporating both digital and analog functions have become increasingly prevalent in the semiconductor industry. Mixed-signal IC test and measurement has grown into a highly specialized field of electrical engineering. It has become harder to hire and train new engineers to become skilled mixed-signal test engineers. The slow learning curve for mixed-signal test engineers is largely due to the shortage of written materials and university-level courses on the subject of mixed-signal testing. While many books have been devoted to the subject of digital test and testability, the same cannot be said for analog and mixed-signal automated test and measurement. This book was written in response ot the shortage of basic course material for mixed-signal test and measurement. The book assumes a solid background in analog and digital circuits as well as a working knowledge of computers and computer programming. A background in digital signal processing and statistical analysis is also helpful, though not absolutely necessary. This material is designed to be useful as both a university textbook and as a reference manual for the beginning professional test engineer. The prerequisite for this book is a junior level course in linear continuous-time and discrete-time systems, as well as exposure ot elementary probability and statistical concepts. More ...
Analog Test and Fault Isolation The problems that you will encounter when you try to test analog circuits with an ATE. The course will show how accuracies and resolutions can affect your test results. You will also learn to deal with analog simulation and fault simulation issues. The IEEE-1149.4 Mixed Signal Testability as well as the IEEE-1149.6 mechanisms will also be explored. Details
  Assessing Fault Model and Test Quality Assessing Fault Model and Test Quality reports original research on the nature of logical fault models and their interactions with ATPG algorithms. The monograph condenses an extensive survey of literature pertaining to testing, test quality, defect level modeling, ordered binary decision diagrams, and other related topics into a cohesive treatment of the general question of measuring the `goodness' of a test. Novel discoveries concerning graphical function representation are recounted. Methods of IC defect level prediction and correlation are reviewed, and a new technique is introduced which inherently addresses more statistically significant sets of test data than was previously possible. The tools introduced in Assessing Fault Model and Test Quality form the basis for the study of many interesting open questions in the areas of test generation, design for testability, design verification, and other disciplines as is shown with the example data that it reports. More ...
ATE Selection, Design and Programming This course covers every aspect of a test engineer's responsibility. Participants will learn how to select an automatic test equipment (ATE) from the number of choices and generically different types available. You will learn how to build an ATE from instrumentation and other building blocks. You will learn the bussing requirements of the IEEE 488, VXIbus, and PC-based instruments. You will also learn the software issues. The course will teach you how to approach a functional test programming activity for digital circuits. (In the longer, three-day course, analog test programming is also covered.) Finally, you will learn test management issues, such as test program development estimation, acquisition and quality assurance. Details
  Boundary-Scan Test A Practical Approach This book will act an introduction to as well as a practical guide to Boundary-Scan testing. The ever increasing miniaturization of digital electronic components is hampering the conventional testing of Printed Circuit Boards (PCBs) by means of bed-of-nails fixtures. Basically this is caused by the very high scale of integration of ICs, through which packages with hundreds of pins at very small pitches of down to a fraction of a millimeter, have become available. As a consequence, the trace distances between the copper tracks on a printed circuit board came down to the same value. Not only have the required small physical dimensions of the test nails made conventional testing unfeasible, the complexity to provide test signals for many hundreds of test nails has grown beyond manageable limits. Following the evolution in the IC test technology, Boundary-Scan testing has become the new approach to PCB testing. By taking precautions in the design of the IC (design for testability), testing on a PCB level could be simplified to a great extent. This condition has been essential for the success of the introduction of a Boundary-Scan Test (BST) at board level. This book will aid a company to introduce the Boundary-Scan Test. IC design and test engineers alike will find the book an important introduction and guide to using the Boundary-Scan Test in their work. Engineering managers can also use this book to gain an insight to the impact that the Boundary-Scan Test will make on their organization. More ...
  Built In Test for VLSI: Pseudorandom Techniques This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing. More ...
Cost Effective Tests Using ATE, DFT and BIST The two main reasons to test are 1) to eliminate failures escaping to your customers and 2) to reduce the life cycle cost of a product by eliminating penalty costs associated with delivering potentially faulty units. Many people have traded one of these requirements for the other, but with the advent of more sophisticated automatic test equipment (ATE), more attention paid to design for testability (DFT) and utilizing built-in self test (BIST), it is possible to do both. This tutorial provides a thorough understanding of each of these tools and strategies for more comprehensive and cost-effective testing. The course will combine the technical aspects of testing today’s complex circuits with the economics demanded by lower costs, faster times to market and a higher rate of obsolescence for both electronic products and test equipment. Details
  Delay Fault Testing for VLSI Circuits With the ever-increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality level. The need for testing timing defects is further expected to grow with the current design trend of moving towards deep submicron devices. After a long period of prevailing belief that high stuck-at fault coverage is sufficient to guarantee high quality of shipped products, the industry is now forced to rethink other types of testing. Delay testing has been a topic of extensive research both in industry and in academia for more than a decade. As a result, several delay fault models and numerous testing methodologies have been proposed. Delay Fault Testing for VLSI Circuits presents a selection of existing delay testing research results. It combines introductory material with state-of-the-art techniques that address some of the current problems in delay testing. Delay Fault Testing for VLSI Circuits covers some basic topics such as fault modeling and test application schemes for detecting delay defects. It also presents summaries and conclusions of several recent case studies and experiments related to delay testing. A selection of delay testing issues and test techniques such as delay fault simulation, test generation, design for testability and synthesis for testability are also covered. Delay Fault Testing for VLSI Circuits is intended for use by CAD and test engineers, researchers, tool developers and graduate students. It requires a basic background in digital testing. The book can used as supplementary material for a graduate-level course on VLSI testing. More ...
  Design for AT-Speed Test, Diagnosis and Measurement Design for AT-Speed Test, Diagnosis and Measurement offers practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design makes this book a `must read' before any DFT is attempted. More ...
Design for Excellence This course will teach you how to design a product that is manufacturable, testable, reliable, useable, electromagnetically compatible, maintainable and supportable. In short, an electronic product that not only functions but is made to be of excellent value to you and to your customer. Details
Design for Testability and Built-In Self Test for Boards and Systems You will be exposed to structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, and by the recently released IEEE-1687 standards. The course will cover memory BIST, logic BIST and analog BIST and how they can be used for board and system test. It will also cover built-in test (BIT) software, and its goal to provide diagnostic information. You will obtain convincing reasons for utilizing DFT and BIST techniques in your organization's board and system design. Details
Design for Testability and for Built-in Self Test In this comprehensive course you will learn all aspects of Design for Testability (DFT), from what it is, why you might need it, why someone would object to it, and what it can and cannot accomplish. You will learn how today's technology has become elusive to certain failure modes and how important it is to expose them through more testable designs. This 3-day class will encompass DFT techniques for ICs, ASICs, SoCs, FPGAs, boards, systems, and even prognostic health management. First you will learn some simple techniques to enhance observability and controllability. You will learn how you can access hundreds of internal points with as few as four additional edge connector pins. You will learn specific guidelines for both digital and analog circuit testability. You will learn structured testability techniques, such as internal and boundary-scan. You will come away with a deep understanding of the IEEE 1149.1 (JTAG) standard's operation, use and even its limitations. You will also learn later standards, such as IEEE-1149.4, .6, .7 as well as IEEE-1500, 1532, 1581 and 1687. You will also learn some new techniques in testability, including IDDQ testing and I/O Mapping. In the second part of the course, you will learn what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. With these building blocks you will be able to evaluate a number of BIST architectures for Logic BIST and Memory BIST. You will learn BIT Software techniques and consider the effect false alarms have on BIT. You will finally be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions. Details
  Design of Systems on a Chip: Design and Test This text provides the Design for Testability information crucial to designers of Systems on a Chip (SOC). More ...
  Digital Circuit Testing and Testability This is an easy to use introduction to the practices and techniques in the field of digital circuit testing. The author writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter. More ...
  Digital Circuit Testing: A Guide to DFT and Other Technologies Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to these and other testing techniques. For each technique introduced, the author provides real-world examples so the reader can achieve a working knowledge of how to choose and apply these increasingly important testing methods. More ...
  Digital Hardware Testing Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path. Contents:Faults in Digital Circuits. Bridging Faults in Random Logic. Open Circuit Faults in Random Logic. Fault Simulation and Test Generation. Testing of Structured Designs (PLAs). Memory Testing. Testing of Sequential Circuits. Microprocessor Testing. Design for Testability. Current Testing. Special Test Methods. More ...
  Digital Systems Testing and Testable Design This widely-used textbook provides comprehensive, state-of-the-art coverage of digital systems testing and testable design. Considered a definitive text in this area, the book includes in-depth discussions of the following topics: Test generation Fault modeling for classic and new technologies Simulation Fault simulation Design for testability Built-in self-test (BIST) Diagnosis All topics are covered extensively, from fundamental concepts to advanced techniques. Successfully used world-wide at leading universities, the book is appropriate for graduate-level and senior-level undergraduate courses. Numerous examples and problems help make the learning process easier for the reader. Test engineers, ASIC and system designers, and CAD developers will find it an invaluable tool to keep current with recent changes in the field. More ...
  Embedded Processor-Based Self-Test Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit’s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design. Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment. More ...
  Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits Today's electronic design and test engineers deal with several types of subsystems, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods. This book provides a careful selection of essential topics on all three types of circuits. The outcome of testing is product quality, which means `meeting the user's needs at a minimum cost.' The book includes test economics and techniques for determining the defect level of VLSI chips. Besides being a textbook for a course on testing, it is a complete testability guide for an engineer working on any kind of electronic device or system or a system-on-a-chip. More ...
Failure Mode and Effects Analysis (FMEA) You will learn how to prepare and utilize FMEA to improve reliability, safety, testability, and maintainability. This course will describe FMEA methodology and its multiple uses for a more reliable, testable and maintainable product. Details
How to Design for Testability (DFT) for Today's Boards and Systems Detailed review of the various guidelines covered in the SMTA/TMAG Testability Guidelines. Part 1 of the Webtorial will introduce attendees to the issues surrounding testing of electronic circuit boards and systems. It introduces testing concept and the mix of testers normally used. This includes the JTAG/IEEE-1149.1 boundary scan as well as built-in self test (BIST). With a combination of these technologies, the idea of non-intrusive board (and system) test is explored. The Webtorial takes the view that DFT is the best way to improve test performance and cost effectiveness. Towards that end Part 2 provides specific DFT guidelines. It concludes with exploring new standards and developments in DFT that will improve testing of boards and systems in the future. Details
  IDDQ Testing of VLSI Circuits Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice. More ...
Integrated Diagnostics and Artificial Intelligence How integrated diagnostics and artificial intelligence (AI) can be used to improve product support. You will learn the basic principals of artificial intelligence and how they apply to test and diagnosis. You will also learn diagnostic concepts, including dependency modeling and optimizations. Details
  Microelectronic Reliability, Vol 1 Let twelve specialists show you how to test, analyze, and achieve better microelectronic reliability of silicon and GaAs devices. Microelectronic Reliability, Volume I: Reliability, Test, and Diagnostics offers you detailed, original works on the topics most vital to both device and equipment reliability and manufacturing yield. Broad enough to serve as an effective textbook and in-depth enough for practicing engineers, this text also makes an ideal reference for managers who need a quick overview of current reliability, test, and failure analysis issues. Supported by 600 references, 147 figures, and 39 tables, this encyclopedic guide shows you how to identify the thermal, chemical, and mechanical processes that influence the incidence and severity of failure mechanisms. This coverage outlines techniques for assessing the susceptibility to failure of various devices. Detailing the theory and operation of current failure analysis tools, the text also gives you instrument price ranges and example analyses. Combined with the sweeping overview and comprehensive bibliography found in Microelectronic Reliability Volume II, this text gives you the only source you need to meet today's ever-improving standards for quality and reliability of advanced microelectronic technology. Contents: Preface. Introduction. Statistical Aspects for Reliability. Failure Mechanisms in Microelectronic Devices. Testability for Functional Verification and Diagnostics. Automatic Testing. Manufacturing Process Control. GaAs Reliability and Test. Appendix A: Advanced Failure Analysis Instrumentation. List of Acronyms. Glossary. Index. More ...
  Neural Models and Algorithms for Digital Testing Neural Models and Algorithms for Digital Testing presents a novel solution to a difficult problem, namely, test generation for digital logic circuits. An optimization approach to this problem has only recently been attempted. The authors propose a new and unconventional modeling technique for digital circuits. The input and output signal states of a logic gate are related through an energy function such that the minimum energy states correspond to the gate's logic function. There are at least two advantages to this new approach. First, since the function of the circuit is expressed as a mathematical expression, new techniques can be used to solve a problem like test generation. Second, the non-causal form of the model allows effective use of parallel processing. The authors present the mathematical basis for models and discuss their fundamental properties. Based on the same circuit models, test generation algorithms that can exploit fine-grain parallel computing, relaxation techniques, quadratic 0-1 programming and graph-theoretic techniques are presented. In addition to its practical value, the proposed problem formulation leads to interesting theoretical contributions. As a further application of the model, the intractability of the test generation problem is considered. Using the neural network models, a new class of circuits in which this problem is solvable in polynomial time is presented. This contribution is especially important since it leads to design styles for easily-testable digital circuits and provides a possible step toward design for testability. More ...
  SMTA Testability Guidelines 101C - Single User Copy Led by SMTA Testability Committee chair Louis Y. Ungar of A.T.E. Solutions, Inc., these SMTA Testability Guidelines were developed by various Task Forces. The work of the various Task Forces is featured as separate chapters. A general format applies to each task force, and it was intended to assist the reader in dealing with the testability considerations that need to go into the design, development, and test of a product. Each chapter begins with an introduction intended to put into perspective the enumerated guidelines that follow. Finally, a glossary is provided, and a reference section is included for further research. These guidelines can now be downloaded under either a Single-User license (only one copy – no sharing) or under a Site-License (everyone at your physical location –site) can use it both in hard or soft form. You may purchase a Single-User copy now, and update at a later time – but you will save $39.95 if you buy the Site-License copy now. Instead of this Single User Copy, select the Site License copy and save! You can compare the licenses here before you buy. More ...
  SMTA Testability Guidelines 101C - Site License for Everyone at your Facility If you already own the Single User Copy, you can upgrade to include everyone at your facility or you can save $39.95 by buying the more versatile Site License now. Led by SMTA Testability Committee chair Louis Y. Ungar of A.T.E. Solutions, Inc., these SMTA Testability Guidelines were developed by various Task Forces. The work of the various Task Forces is featured as separate chapters. A general format applies to each task force, and it was intended to assist the reader in dealing with the testability considerations that need to go into the design, development, and test of a product. Each chapter begins with an introduction intended to put into perspective the enumerated guidelines that follow. Finally, a glossary is provided, and a reference section is included for further research. Download this valuable document and have all your designs testable - today. You can compare the licenses here before you buy. More ...
Software Design for Testability (SDFT) The latest theory and practice of Software Design for Testability (SDFT) will be explained, primarily through comparisons and analogies to the well-established discipline of hardware DFT. Details
Standards in Test You will be introduced to most of the Military and Commercial Standards that affect the way test is performed and interpreted by both military and commercial concerns. Details
  System-level Test and Validation of Hardware/Software Systems New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability. More ...
  Test and Design-For-Testability in Mixed-Signal Integrated Circuits Test and Design-for-Testability in Mixed-Signal Integrated Circuits deals with test and design for test of analog and mixed-signal integrated circuits. Especially in System-on-Chip (SoC), where different technologies are intertwined (analog, digital, sensors, RF); test is becoming a true bottleneck of present and future IC projects. Linking design and test in these heterogeneous systems will have a tremendous impact in terms of test time, cost and proficiency. Although it is recognized as a key issue for developing complex ICs, there is still a lack of structured references presenting the major topics in this area. The aim of this book is to present basic concepts and new ideas in a manner understandable for both professionals and students. Since this is an active research field, a comprehensive state-of-the-art overview is very valuable, introducing the main problems as well as the ways of solution that seem promising, emphasizing their basis, strengths and weaknesses. In essence, several topics are presented in detail. First of all, techniques for the efficient use of DSP-based test and CAD test tools. Standardization is another topic considered in the book, with focus on the IEEE 1149.4. Also addressed in depth is the connecting design and test by means of using high-level (behavioural) description techniques, specific examples are given. Another issue is related to test techniques for well-defined classes of integrated blocks, like data converters and phase-locked-loops. Besides these specification-driven testing techniques, fault-driven approaches are described as they offer potential solutions which are more similar to digital test methods. Finally, in Design-for-Testability and Built-In-Self-Test, two other concepts that were taken from digital design, are introduced in an analog context and illustrated for the case of integrated filters. In summary, the purpose of this book is to provide a glimpse on recent research results in the area of testing mixed-signal integrated circuits, specifically in the topics mentioned above. Much of the work reported herein has been performed within cooperative European Research Projects, in which the authors of the different chapters have actively collaborated. It is a representative snapshot of the current state-of-the-art in this emergent field. More ...
  Testability Concepts for Digital ICs: The Macro Test Approach Throughout the 1980s and 1990s, the theory and practice of testing electronic products has changed considerably. Quality and testing have become inextricably linked and both are fundamental to the generation of revenue to a company, helping the company to remain profitable and therefore survive. Testing plays an important role in assessing the quality of a product. The tester acts as a filter, separating good products from bad. Unfortunately, the tester can pass bad products and fail good products, and the generation of high quality tests has become complex and time consuming. To achieve significant reduction in time and cost of testing, the role and responsibility of testing has to be considered across an entire organization and product development process. Testability Concepts for Digital ICs: The Macro Test Approach considers testability aspects for digital ICs. The strategy taken is to integrate the testability aspects into the design and manufacturing of ICs and, for each IC design project, to give a precise definition of the boundary conditions, responsibilities, interfaces and communications between persons, and quality targets. Macro Test, a design-for-Testability approach, provides a manageable test program route. Using the Macro Test approach, one can explore alternative solutions to satisfy pre-defined levels of performance (e.g. defect detection, defect location, test application) within a pre-defined cost budget and time scale. Testability Concepts for Digital ICs is the first book to present a tried and proven method of using a Macro approach to testing complex ICs and is of particular interest to all test engineers, IC designers and managers concerned with producing high quality ICs. More ...
  Testing and Testable Design of High-Density Random-Access Memories Testing and Testable Design of High-Density Random-Access Memories deals with the study of fault modeling, testing and testable design of semiconductor random-access memories. It is written primarily for the practicing design engineer and the manufacturer of random-access memories (RAMs) of the modern age. It provides useful exposure to state-of-the-art testing schemes and testable design approaches for RAMs. It is also useful as a supplementary text for undergraduate courses on testing and testability of RAMs. Testing and Testable Design of High-Density Random-Access Memories presents an integrated approach to state-of-the-art testing and testable design techniques for RAMs. These new techniques are being used for increasing the memory testability and for lowering the cost of test equipment. Semiconductor memories are an essential component of digital computers - they are used as primary storage devices. They are used in almost all home electronic equipment, in hospitals and for avionics and space applications. From hand-held electronic calculators to supercomputers, we have seen generations of memories that have progressively become smaller, smarter and cheaper. For the past two decades there has been vigorous research in semiconductor memory design and testing. Such research has resulted in bringing the dynamic RAM (DRAM) to the forefront of the microelectronics industry in terms of achievable integration levels, high performance, high reliability, low power and low cost. The DRAM is regarded as the technological driver for the commercial microelectronics industry. Testing and Testable Design of High-Density Random-Access Memories deals with real- world examples that will be useful to readers. This book also provides college and university students with a systematic exposure to a wide spectrum of issues related to RAM testing and testable design. More ...
  The Design for Testability and Built-In Self Test (DFT/BIST) Library Collection We selected 21 of the best books on the subjec for your company library with the intent of providing all the information you need to understand Design for Testability and Built-In Self-Test for analog, digital, mixed signal, board-leve, system-level,system-on-a-chip and even for a formal approach. The combined list price of individual books is considerably higher. We update the selections based on availability and how they apply to current needs. See a list in The Test Library Collection More ...
The Economics of Test and Testability Why test is a solution to an economic problem How non-technical management views return on investment (ROI) and how to translate technical benefits to these terms Existing formulas for the cost and benefits of IC, board, and system tests How behavioral economics applies to test and what we can learn from it. Details
  The Testability Director This low priced software is used to motivate and evaluate testability practices in your organization. It contains hundreds of guidelines for meeting different types of testability criteria, including ASIC design, Analog, Digital, System Level and Built-In Test. The software runs with Microsoft Excel and many popular spreadsheet programs and contains tutorials on interpreting and scoring each criterion. It is truly the painless way to bring Design for Testability into your organization. See it at Testability Director Web Page More ...
VLSI Simulation and Test Generation The stuck-at models used in simple logic is becoming obsolete when we wish to test Very Large Scale Integrated circuits. You will learn new approaches to test that can be used to test highly complex circuits. Details
  VLSI Test Principles and Architectures: Design for Testability This book combines in a unique way insight into industry practices commonly found in commercial DFT tools but not discussed in textbooks, and a sound treatment of the future fundamentals. The comprehensive review of future test technology trends, including self-repair, soft error protection, MEMS testing, and RF testing, leads students and researchers to advanced DFT research. More ...
WebCourse - ATE 101 - Overview of Test, ATE & Testability A participant who has little or no background in test can leave this course with a thorough understanding of the issues. While the course provides few solutions, it is imperative that anyone making decisions concerning test and testability should first attend this course. Details
WebCourse - ATE 301 - ATE Test Programming This course will teach you what is involved in developing a test program for an ATE. If you have never written a test program before, the course will illustrate the difficulties and point out traps that can make test programming a nightmare. For those who have experienced these problems, the course will provide a structured approach that will help avoid these problems in the future. Details
WebCourse - Design for Testability 101 - Who, What, When, Why, How Much You will learn why Design for Testabilty (DFT) is an invaluable method to reduce test development costs. As long as DFT is performed early in the design stage, the return on investment (ROI) is substantial. You will learn how to translate techinical issues involving testability to economic issues understood by non-technical management. Details
WebCourse - Design for Testability 201 - Techniques for ICs, Boards and Systems You will learn specific Design for Testabilty (DFT) techniques for making your circuit more testable, whether the circuit is an Integrated Circuit, Circuit Board, or a System. This course provides the "How" that was not covered in DFT 101. You will learn easy to apply techniques to circuits that will reap substantial benefits when it comes time to test the circuit. Details
WebCourse - Design for Testability 301 - JTAG/Boundary Scan/IEEE 1149.1 You will learn the details of Boundary Scan, often called, JTAG and officially called the IEEE-1149.1 standard. While you may have come across this concept, you may still be a bit unsure if you have a clear understanding. In this webinar we look under the hood and you will learn the intricate details of how this technology works. Details
WebCourse - Design for Testability 401 - System Level Testability and Diagnosability For system level, testability isn't only failure detection. You need to concern yourself with repair and before that can happen, you need to accurately and unambigously determine the root cause of the system failure. That root cause should involve a single replaceable subsystem or board in nearly all cases. You will learn how to approach this in a logical fashion. Details
WebCourse - Design for Testability 501 - Advanced DFT Techniques Boundary Scan pioneered a new approach to testability for board level. It is, however, important to integrate this with other forms of assembly. For today's complex circuits it may not be sufficient to test the boundary of the IC. Rather we will need to test inside the IC even when the IC is already mounted on a circuit board and when that board is already part of a module or system. This webinar will teach you about newer tools and the integration of those tools with traditional testability approaches. Details